Matching Items (5)
Description
Gallium-based liquid metals are of interest for a variety of applications including flexible electronics, soft robotics, and biomedical devices. Still, nano- to microscale device fabrication with these materials is challenging because of their strong adhesion to a majority of substrates. This unusual high adhesion is attributed to the formation of a thin oxide shell; however, its role in the adhesion process has not yet been established. In the first part of the thesis, we described a multiscale study aiming at understanding the fundamental mechanisms governing wetting and adhesion of gallium-based liquid metals. In particular, macroscale dynamic contact angle measurements were coupled with Scanning Electron Microscope (SEM) imaging to relate macroscopic drop adhesion to morphology of the liquid metal-surface interface. In addition, room temperature liquid-metal microfluidic devices are also attractive systems for hyperelastic strain sensing. Currently two types of liquid metal-based strain sensors exist for inplane measurements: single-microchannel resistive and two-microchannel capacitive devices. However, with a winding serpentine channel geometry, these sensors typically have a footprint of about a square centimeter, limiting the number of sensors that can be embedded into. In the second part of the thesis, firstly, simulations and an experimental setup consisting of two GaInSn filled tubes submerged within a dielectric liquid bath are used to quantify the effects of the cylindrical electrode geometry including diameter, spacing, and meniscus shape as well as dielectric constant of the insulating liquid and the presence of tubing on the overall system's capacitance. Furthermore, a procedure for fabricating the two-liquid capacitor within a single straight polydiemethylsiloxane channel is developed. Lastly, capacitance and response of this compact device to strain and operational issues arising from complex hydrodynamics near liquid-liquid and liquid-elastomer interfaces are described.
ContributorsLiu, Shanliangzi (Author) / Rykaczewski, Konrad (Thesis advisor) / Alford, Terry (Committee member) / Herrmann, Marcus (Committee member) / Hildreth, Owen (Committee member) / Arizona State University (Publisher)
Created2015
Description
Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
ContributorsSivakumar, Balasubramanian (Author) / Farahani, Bahar Jalali (Thesis advisor) / Garrity, Douglas (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
Description
Shunt capacitors are often added in transmission networks at suitable locations to improve the voltage profile. In this thesis, the transmission system in Arizona is considered as a test bed. Many shunt capacitors already exist in the Arizona transmission system and more are planned to be added. Addition of these shunt capacitors may create resonance conditions in response to harmonic voltages and currents. Such resonance, if it occurs, may create problematic issues in the system. It is main objective of this thesis to identify potential problematic effects that could occur after placing new shunt capacitors at selected buses in the Arizona network. Part of the objective is to create a systematic plan for avoidance of resonance issues.
For this study, a method of capacitance scan is proposed. The bus admittance matrix is used as a model of the networked transmission system. The calculations on the admittance matrix were done using Matlab. The test bed is the actual transmission system in Arizona; however, for proprietary reasons, bus names are masked in the thesis copy in-tended for the public domain. The admittance matrix was obtained from data using the PowerWorld Simulator after equivalencing the 2016 summer peak load (planning case). The full Western Electricity Coordinating Council (WECC) system data were used. The equivalencing procedure retains only the Arizona portion of the WECC.
The capacitor scan results for single capacitor placement and multiple capacitor placement cases are presented. Problematic cases are identified in the form of ‘forbidden response. The harmonic voltage impact of known sources of harmonics, mainly large scale HVDC sources, is also presented.
Specific key results for the study indicated include:
• The forbidden zones obtained as per the IEEE 519 standard indicates the bus 10 to be the most problematic bus.
• The forbidden zones also indicate that switching values for the switched shunt capacitor (if used) at bus 3 should be should be considered carefully to avoid resonance condition from existing.
• The highest sensitivity of 0.0033 per unit for HVDC sources of harmonics was observed at bus 7 when all the HVDC sources were active at the same time.
For this study, a method of capacitance scan is proposed. The bus admittance matrix is used as a model of the networked transmission system. The calculations on the admittance matrix were done using Matlab. The test bed is the actual transmission system in Arizona; however, for proprietary reasons, bus names are masked in the thesis copy in-tended for the public domain. The admittance matrix was obtained from data using the PowerWorld Simulator after equivalencing the 2016 summer peak load (planning case). The full Western Electricity Coordinating Council (WECC) system data were used. The equivalencing procedure retains only the Arizona portion of the WECC.
The capacitor scan results for single capacitor placement and multiple capacitor placement cases are presented. Problematic cases are identified in the form of ‘forbidden response. The harmonic voltage impact of known sources of harmonics, mainly large scale HVDC sources, is also presented.
Specific key results for the study indicated include:
• The forbidden zones obtained as per the IEEE 519 standard indicates the bus 10 to be the most problematic bus.
• The forbidden zones also indicate that switching values for the switched shunt capacitor (if used) at bus 3 should be should be considered carefully to avoid resonance condition from existing.
• The highest sensitivity of 0.0033 per unit for HVDC sources of harmonics was observed at bus 7 when all the HVDC sources were active at the same time.
ContributorsPatil, Hardik U (Author) / Heydt, Gerald T (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2015
Description
Two nested capacitors can produce work if the electric fields are not aligned, and the purpose of this research was to explore the possibility of using that generation instead of DC motors. The work the capacitors produce is determined by the strength of the fields and materials that is composed of. The power density of the object is then determined by the volume. As the electric field increases in strength, the power increases, so to create a very strong internal field. The nested capacitors use a dielectric to prevent breakdown from the strength of the field. Additionally, as the nested capacitors decrease in size, their power density increases rapidly \u2014 becoming close to a dc motor's power density around the 500mm^2 size. When the result was simulated, it was discovered that the electric field was not contained to the dielectric and would result in sparking. Several other concerns would need to be addressed for this to become a viable solution.
ContributorsFryda, George Andrew (Author) / Singh, Anoop (Thesis director) / Yu, Hongbin (Committee member) / Mechanical and Aerospace Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.
ContributorsKao, Wei-Chieh (Author) / Goryll, Michael (Thesis advisor) / Chowdhury, Srabanti (Committee member) / Yu, Hongbin (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2015