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In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Layer structured two dimensional (2D) semiconductors have gained much interest due to their intriguing optical and electronic properties induced by the unique van der Waals bonding between layers. The extraordinary success for graphene and transition metal dichalcogenides (TMDCs) has triggered a constant search for novel 2D semiconductors beyond them. Gallium

Layer structured two dimensional (2D) semiconductors have gained much interest due to their intriguing optical and electronic properties induced by the unique van der Waals bonding between layers. The extraordinary success for graphene and transition metal dichalcogenides (TMDCs) has triggered a constant search for novel 2D semiconductors beyond them. Gallium chalcogenides, belonging to the group III-VI compounds, are a new class of 2D semiconductors that carry a variety of interesting properties including wide spectrum coverage of their bandgaps and thus are promising candidates for next generation electronic and optoelectronic devices. Pushing these materials toward applications requires more controllable synthesis methods and facile routes for engineering their properties on demand.

In this dissertation, vapor phase transport is used to synthesize layer structured gallium chalcogenide nanomaterials with highly controlled structure, morphology and properties, with particular emphasis on GaSe, GaTe and GaSeTe alloys. Multiple routes are used to manipulate the physical properties of these materials including strain engineering, defect engineering and phase engineering. First, 2D GaSe with controlled morphologies is synthesized on Si(111) substrates and the bandgap is significantly reduced from 2 eV to 1.7 eV due to lateral tensile strain. By applying vertical compressive strain using a diamond anvil cell, the band gap can be further reduced to 1.4 eV. Next, pseudo-1D GaTe nanomaterials with a monoclinic structure are synthesized on various substrates. The product exhibits highly anisotropic atomic structure and properties characterized by high-resolution transmission electron microscopy and angle resolved Raman and photoluminescence (PL) spectroscopy. Multiple sharp PL emissions below the bandgap are found due to defects localized at the edges and grain boundaries. Finally, layer structured GaSe1-xTex alloys across the full composition range are synthesized on GaAs(111) substrates. Results show that GaAs(111) substrate plays an essential role in stabilizing the metastable single-phase alloys within the miscibility gaps. A hexagonal to monoclinic phase crossover is observed as the Te content increases. The phase crossover features coexistence of both phases and isotropic to anisotropic structural transition.

Overall, this work provides insights into the controlled synthesis of gallium chalcogenides and opens up new opportunities towards optoelectronic applications that require tunable material properties.
ContributorsCai, Hui, Ph.D (Author) / Tongay, Sefaattin (Thesis advisor) / Dwyer, Christian (Committee member) / Zhuang, Houlong (Committee member) / Arizona State University (Publisher)
Created2018