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In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
Description

In this thesis, I discuss the development of a novel physical design flow introducing standard-cell neurons for ASIC design. Standard-cell neurons are implemented on silicon as a circuit that realizes a threshold function. Each cell contains flash transistors, the threshold voltages of which correspond to the weights of the threshold

In this thesis, I discuss the development of a novel physical design flow introducing standard-cell neurons for ASIC design. Standard-cell neurons are implemented on silicon as a circuit that realizes a threshold function. Each cell contains flash transistors, the threshold voltages of which correspond to the weights of the threshold function. Since the threshold voltages are programmed after fabrication, any sequential logic containing a standard-cell neuron is a logical black box upon delivery to the foundry. Additionally, previous research has shown significant reductions in delay, power, and area with the utilization of these flash transistor (FTL) cells. This paper aims to reinforce this prior research by demonstrating the first automatically synthesized, placed, and routed secure RISC-V core.

ContributorsGrier, Willem (Author) / Vrudhula, Sarma (Thesis director) / Singh, Gian (Committee member) / Barrett, The Honors College (Contributor) / Computer Science and Engineering Program (Contributor) / Dean, W.P. Carey School of Business (Contributor)
Created2022-12