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Description
Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization.
To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.
The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.
The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.
To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.
The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.
The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.
ContributorsRajabi, Saba (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to current followed by a transimpedance amplifier to convert the current to a useful voltage. Different systems create different requirements for each receiver. High speed digital communication require high throughput with enough sensitivity to keep the bit error rate low. Instrumentation receivers have a lower bandwidth, but higher gain and sensitivity requirements. In this thesis an optical receiver for use in instrumentation in presented. It is an entirely monolithic design with the photodiodes on the same substrate as the CMOS circuitry. This allows for it to be built into a focal-plane array, but it places some restriction on the area. It is also designed for in-situ testing and must be able to cancel any low frequency noise caused by ambient light. The area restrictions prohibit the use of a DC blocking capacitor to reject the low frequency noise. In place a servo loop was wrapped around the system to reject any DC offset. A modified Cherry-Hooper architecture was used for the transimpedance amplifier. This provides the flexibility to create an amplifier with high gain and wide bandwidth that is independent of the input capacitance. The downside is the increased complexity of the design makes stability paramount to the design. Another drawback is the high noise associated with low input impedance that decouples the input capacitance from the bandwidth. This problem is compounded by the servo loop feed which leaves the output noise of some amplifiers directly referred to the input. An in depth analysis of each circuit block's noise contribution is presented.
ContributorsLaFevre, Kyle (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Vermeire, Bert (Committee member) / Arizona State University (Publisher)
Created2011
Description
The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static (QS) description of the MOSFET. The model is implemented in two widely used circuit simulators and tested for speed and convergence. It is verified by comparison with technology computer aided design (TCAD) simulations and experimental data, and by application of a recently developed benchmark test for NQS MOSFET models. In addition, a new and simple technique to characterize NQS and gate resistance, Rgate, MOS model parameters from measured data has been presented. In the process of experimental model verification, the effects of bulk resistance on MOSFET characteristics is investigated both theoretically and experimentally to separate it from the NQS effects.
ContributorsZhu, Zeqin (Author) / Gildenblat, Gennady (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Barnaby, Hugh (Committee member) / Mcandrew, Colin C (Committee member) / Arizona State University (Publisher)
Created2012
Description
The front end of almost all ADCs consists of a Sample and Hold Circuit in order to make sure a constant analog value is digitized at the end of ADC. The design of Track and Hold Circuit (THA) mainly focuses on following parameters: Input frequency, Sampling frequency, dynamic Range, hold pedestal, feed through error. This thesis will discuss the importance of these parameters of a THA to the ADCs and commonly used architectures of THA. A new architecture with SiGe HBT transistors in BiCMOS 130 nm technology is presented here. The proposed topology without complicated circuitry achieves high Spurious Free Dynamic Range(SFDR) and Total Harmonic Distortion (THD).These are important figure of merits for any THA which gives a measure of non-linearity of the circuit. The proposed topology is implemented in IBM8HP 130 nm BiCMOS process combines typical emitter follower switch in bipolar THAs and output steering technique proposed in the previous work. With these techniques and the cascode transistor in the input which is used to isolate the switch from the input during the hold mode, better results have been achieved. The THA is designed to work with maximum input frequency of 250 MHz at sampling frequency of 500 MHz with input currents not more than 5mA achieving an SFDR of 78.49 dB. Simulation and results are presented, illustrating the advantages and trade-offs of the proposed topology.
ContributorsRao, Nishita Ramakrishna (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact NVM. Current technology nodes are nearing the physical limits of scaling, preventing flash from improving. To combat the limitations of flash and to appease consumer demand for progressively faster and denser NVM, new technologies are needed. One possible candidate for the replacement of NAND Flash is programmable metallization cells (PMC). PMC are a type of resistive memory, meaning that they do not rely on charge storage to maintain a logic state. Depending on their application, it is possible that devices containing NVM will be exposed to harsh radiation environments. As part of the process for developing a novel memory technology, it is important to characterize the effects irradiation has on the functionality of the devices.
This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario.
The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory.
This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario.
The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory.
ContributorsTaggart, Jennifer Lynn (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2015
Description
Counterfeiting of goods is a widespread epidemic that is affecting the world economy. The conventional labeling techniques are proving inadequate to thwart determined counterfeiters equipped with sophisticated technologies. There is a growing need of a secure labeling that is easy to manufacture and analyze but extremely difficult to copy. Programmable metallization cell technology operates on a principle of controllable reduction of a metal ions to an electrodeposit in a solid electrolyte by application of bias. The nature of metallic electrodeposit is unique for each instance of growth, moreover it has a treelike, bifurcating fractal structure with high information capacity. These qualities of the electrodeposit can be exploited to use it as a physical unclonable function. The secure labels made from the electrodeposits grown in radial structure can provide enhanced authentication and protection from counterfeiting and tampering.
So far only microscale radial structures and electrodeposits have been fabricated which limits their use to labeling only high value items due to high cost associated with their fabrication and analysis. Therefore, there is a need for a simple recipe for fabrication of macroscale structure that does not need sophisticated lithography tools and cleanroom environment. Moreover, the growth kinetics and material characteristics of such macroscale electrodeposits need to be investigated. In this thesis, a recipe for fabrication of centimeter scale radial structure for growing Ag electrodeposits using simple fabrication techniques was proposed. Fractal analysis of an electrodeposit suggested information capacity of 1.27 x 1019. The kinetics of growth were investigated by electrical characterization of the full cell and only solid electrolyte at different temperatures. It was found that mass transport of ions is the rate limiting process in the growth. Materials and optical characterization techniques revealed that the subtle relief like structure and consequently distinct optical response of the electrodeposit provides an added layer of security. Thus, the enormous information capacity, ease of fabrication and simplicity of analysis make macroscale fractal electrodeposits grown in radial programmable metallization cells excellent candidates for application as physical unclonable functions.
So far only microscale radial structures and electrodeposits have been fabricated which limits their use to labeling only high value items due to high cost associated with their fabrication and analysis. Therefore, there is a need for a simple recipe for fabrication of macroscale structure that does not need sophisticated lithography tools and cleanroom environment. Moreover, the growth kinetics and material characteristics of such macroscale electrodeposits need to be investigated. In this thesis, a recipe for fabrication of centimeter scale radial structure for growing Ag electrodeposits using simple fabrication techniques was proposed. Fractal analysis of an electrodeposit suggested information capacity of 1.27 x 1019. The kinetics of growth were investigated by electrical characterization of the full cell and only solid electrolyte at different temperatures. It was found that mass transport of ions is the rate limiting process in the growth. Materials and optical characterization techniques revealed that the subtle relief like structure and consequently distinct optical response of the electrodeposit provides an added layer of security. Thus, the enormous information capacity, ease of fabrication and simplicity of analysis make macroscale fractal electrodeposits grown in radial programmable metallization cells excellent candidates for application as physical unclonable functions.
ContributorsChamele, Ninad (Author) / Kozicki, Michael (Thesis advisor) / Barnaby, Hugh (Thesis advisor) / Newman, Nathan (Committee member) / Arizona State University (Publisher)
Created2017
Description
Metal-Oxide-Semiconductor (MOS) is essential to modern VLSI devices. In the past decades, a wealth of literature has been created to understand the impact of the radiation-induced charges on the devices, i.e., the creation of electron-hole pairs in the oxide layer which is the most sensitive part of MOS structure to the radiation effect. In this work, both MOS and MNOS devices were fabricated at ASU NanoFab to study the total ionizing dose effect using capacitance-voltage (C-V) electrical characterization by observing the direction and amounts of the shift in C-V curves and electron holography observation to directly image the charge buildup at the irradiated oxide film of the oxide-only MOS device.C-V measurements revealed the C-V curves shifted to the left after irradiation (with a positive bias applied) because of the net positive charges trapped at the oxide layer for the oxide-only sample. On the other hand, for nitride/oxide samples with positive biased during irradiation, the C-V curve shifted to the right due to the net negative charges trapped at the oxide layer. It was also observed that the C-V curve has less shift in voltage for MNOS than MOS devices after irradiation due to the less charge buildup after irradiation.
Off-axis electron holography was performed to map the charge distribution across the MOSCAP sample. Compared with both pre-and post-irradiated samples, a larger potential drop at the Si/SiO2 was noticed in post-irradiation samples, which indicates the presence of greater amounts of positive charges that buildup the Si/SiO2 interface after the TID exposure.
TCAD modeling was used to extract the density of charges accumulated near the SiO2/Si and SiO2/ Metal interface by matching the simulation results to the potential data from holography. The increase of near-interface positive charges in post-irradiated samples is consistent with the C-V results.
ContributorsChang, Ching Tao (Author) / Barnaby, Hugh (Thesis advisor) / Holbert, Keith (Committee member) / Tongay, Sefaattin (Committee member) / Arizona State University (Publisher)
Created2023
Description
Lateral programmable metallization cells (PMC) utilize the properties of electrodeposits grown over a solid electrolyte channel. Such devices have an active anode and an inert cathode separated by a long electrodeposit channel in a coplanar arrangement. The ability to transport large amount of metallic mass across the channel makes these devices attractive for various More-Than-Moore applications. Existing literature lacks a comprehensive study of electrodeposit growth kinetics in lateral PMCs. Moreover, the morphology of electrodeposit growth in larger, planar devices is also not understood. Despite the variety of applications, lateral PMCs are not embraced by the semiconductor industry due to incompatible materials and high operating voltages needed for such devices. In this work, a numerical model based on the basic processes in PMCs – cation drift and redox reactions – is proposed, and the effect of various materials parameters on the electrodeposit growth kinetics is reported. The morphology of the electrodeposit growth and kinetics of the electrodeposition process are also studied in devices based on Ag-Ge30Se70 materials system. It was observed that the electrodeposition process mainly consists of two regimes of growth – cation drift limited regime and mixed regime. The electrodeposition starts in cation drift limited regime at low electric fields and transitions into mixed regime as the field increases. The onset of mixed regime can be controlled by applied voltage which also affects the morphology of electrodeposit growth. The numerical model was then used to successfully predict the device kinetics and onset of mixed regime. The problem of materials incompatibility with semiconductor manufacturing was solved by proposing a novel device structure. A bilayer structure using semiconductor foundry friendly materials was suggested as a candidate for solid electrolyte. The bilayer structure consists of a low resistivity oxide shunt layer on top of a high resistivity ion carrying oxide layer. Devices using Cu2O as the low resistivity shunt on top of Cu doped WO3 oxide were fabricated. The bilayer devices provided orders of magnitude improvement in device performance in the context of operating voltage and switching time. Electrical and materials characterization revealed the structure of bilayers and the mechanism of electrodeposition in these devices.
ContributorsChamele, Ninad (Author) / Kozicki, Michael (Thesis advisor) / Barnaby, Hugh (Committee member) / Newman, Nathan (Committee member) / Gonzalez-Velo, Yago (Committee member) / Arizona State University (Publisher)
Created2020
Description
Most hardware today is based on von Neumann architecture separating memory from logic. Valuable processing time is lost in shuttling information back and forth between the two units, a problem called von Neumann bottleneck. As transistors are scaled further down, this bottleneck will make it harder to deliver performance in computing power. Adding to this is the increasing complexity of artificial intelligence logic. Thus, there is a need for a faster and more efficient method of computing. Neuromorphic systems deliver this by emulating the massively parallel and fault-tolerant computing capabilities of the human brain where the action potential is triggered by multiple inputs at once (spatial) or an input that builds up over time (temporal). Highly scalable memristors are key in these systems- they can maintain their internal resistive state based on previous current/voltage values thus mimicking the way the strength of two synapses in the brain can vary. The brain-inspired algorithms are implemented by vector matrix multiplications (VMMs) to provide neuronal outputs. High-density conductive bridging random access memory (CBRAM) crossbar arrays (CBAs) can perform VMMs parallelly with ultra-low energy.This research explores a simple planarization technique that could be potentially extended to integrate front-end-of-line (FEOL) processing of complementary metal oxide semiconductor (CMOS) circuitry with back-end-of-line (BEOL) processing of CBRAM CBAs for one-transistor one-resistor (1T1R) Neuromorphic CMOS chips where the transistor is part of the CMOS circuitry and the CBRAM forms the resistor. It is a photoresist (PR) and spin-on glass (SOG) based planarization recipe to planarize CBRAM electrode patterns on a silicon substrate. In this research, however, the planarization is only applied to mechanical grade (MG) silicon wafers without any CMOS layers on them. The planarization achieved was of a very high order (few tens of nanometers). Additionally, the recipe is cost-effective, provides good quality films and simple as only two types of process technologies are involved- lithography and dry etching.
Subsequent processing would involve depositing the CBRAM layers onto the planarized electrodes to form the resistor. Finally, the entire process flow is to be replicated onto wafers with CMOS layers to form the 1T1R circuit.
ContributorsBiswas, Prabaha (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Velo, Yago Gonzalez (Committee member) / Arizona State University (Publisher)
Created2021