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Protection of Flash Memory in the Space Environment

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This is a test plan document for Team Aegis' capstone project that has the goal of mitigating single event upsets in NAND flash memory caused by space radiation.

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2021-05

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Response of metal structures on chalcogenide thin films to thermal, ultraviolet and microwave processing

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Microwave (MW), thermal, and ultraviolet (UV) annealing were used to explore the response of Ag structures on a Ge-Se chalcogenide glass (ChG) thin film as flexible radiation sensors, and Te-Ti chalcogenide thin films as a material for diffusion barriers in

Microwave (MW), thermal, and ultraviolet (UV) annealing were used to explore the response of Ag structures on a Ge-Se chalcogenide glass (ChG) thin film as flexible radiation sensors, and Te-Ti chalcogenide thin films as a material for diffusion barriers in microelectronics devices and processing of metallized Cu. Flexible resistive radiation sensors consisting of Ag electrodes on a Ge20Se80 ChG thin film and polyethylene naphthalate substrate were exposed to UV radiation. The sensors were mounted on PVC tubes of varying radii to induce bending strains and annealed under ambient conditions up to 150 oC. Initial sensor resistance was measured to be ~1012 Ω; after exposure to UV radiation, the resistance was ~104 Ω. Bending strain and low temperature annealing had no significant effect on the resistance of the sensors. Samples of Cu on Te-Ti thin films were annealed in vacuum for up to 30 minutes and were stable up to 500 oC as revealed using Rutherford backscattering spectrometry (RBS) and four-point-probe analysis. X-ray diffractometry (XRD) indicates Cu grain growth up to 500 oC and phase instability of the Te-Ti barrier at 600 oC. MW processing was performed in a 2.45-GHz microwave cavity on Cu/Te-Ti films for up to 30 seconds to induce oxide growth. Using a calibrated pyrometer above the sample, the temperature of the MW process was measured to be below a maximum of 186 oC. Four-point-probe analysis shows an increase in resistance with an increase in MW time. XRD indicates growth of CuO on the sample surface. RBS suggests oxidation throughout the Te-Ti film. Additional samples were exposed to 907 J/cm2 UV radiation in order to ensure other possible electromagnetically induced mechanisms were not active. There were no changes observed using XRD, RBS or four point probing.

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Date Created
2013

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Static behavior of chalcogenide based programmable metallization cells

Description

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization.

To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.

The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.

The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.

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Date Created
2014

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Retention of programmable metallization cells during ionizing radiation exposure

Description

Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact

Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact NVM. Current technology nodes are nearing the physical limits of scaling, preventing flash from improving. To combat the limitations of flash and to appease consumer demand for progressively faster and denser NVM, new technologies are needed. One possible candidate for the replacement of NAND Flash is programmable metallization cells (PMC). PMC are a type of resistive memory, meaning that they do not rely on charge storage to maintain a logic state. Depending on their application, it is possible that devices containing NVM will be exposed to harsh radiation environments. As part of the process for developing a novel memory technology, it is important to characterize the effects irradiation has on the functionality of the devices.

This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario.

The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory.

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Date Created
2015

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Temperature dependent qualities of amorphous silicon and amorphous silicon carbide passivating stacks

Description

Layers of intrinsic hydrogenated amorphous silicon and amorphous silicon carbide

were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and

Layers of intrinsic hydrogenated amorphous silicon and amorphous silicon carbide

were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and FTIR spectra were observed at incremental stages of thermal annealing. By observing the changes in the lifetimes the sample structure responsible for the most thermally robust surface passivation could be determined. These results were correlated to the optical band gap and the position and relative area of peaks in the FTIR spectra related to to silicon-hydrogen bonds in the layers. It was found that due to an increased presence of hydrogen bonded to silicon at voids within the passivating layer, hydrogenated amorphous silicon carbide at the interface of the substrate coupled with a hydrogenated amorphous silicon top layer provides better passivation after high temperature annealing than other device structures.

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Date Created
2016

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Lateral Ag Electrodeposits in Chalcogenide Glass for Physical Unclonable Function Application

Description

Counterfeiting of goods is a widespread epidemic that is affecting the world economy. The conventional labeling techniques are proving inadequate to thwart determined counterfeiters equipped with sophisticated technologies. There is a growing need of a secure labeling that is easy

Counterfeiting of goods is a widespread epidemic that is affecting the world economy. The conventional labeling techniques are proving inadequate to thwart determined counterfeiters equipped with sophisticated technologies. There is a growing need of a secure labeling that is easy to manufacture and analyze but extremely difficult to copy. Programmable metallization cell technology operates on a principle of controllable reduction of a metal ions to an electrodeposit in a solid electrolyte by application of bias. The nature of metallic electrodeposit is unique for each instance of growth, moreover it has a treelike, bifurcating fractal structure with high information capacity. These qualities of the electrodeposit can be exploited to use it as a physical unclonable function. The secure labels made from the electrodeposits grown in radial structure can provide enhanced authentication and protection from counterfeiting and tampering.

So far only microscale radial structures and electrodeposits have been fabricated which limits their use to labeling only high value items due to high cost associated with their fabrication and analysis. Therefore, there is a need for a simple recipe for fabrication of macroscale structure that does not need sophisticated lithography tools and cleanroom environment. Moreover, the growth kinetics and material characteristics of such macroscale electrodeposits need to be investigated. In this thesis, a recipe for fabrication of centimeter scale radial structure for growing Ag electrodeposits using simple fabrication techniques was proposed. Fractal analysis of an electrodeposit suggested information capacity of 1.27 x 1019. The kinetics of growth were investigated by electrical characterization of the full cell and only solid electrolyte at different temperatures. It was found that mass transport of ions is the rate limiting process in the growth. Materials and optical characterization techniques revealed that the subtle relief like structure and consequently distinct optical response of the electrodeposit provides an added layer of security. Thus, the enormous information capacity, ease of fabrication and simplicity of analysis make macroscale fractal electrodeposits grown in radial programmable metallization cells excellent candidates for application as physical unclonable functions.

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Date Created
2017

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Nozzle Design for Vacuum Aerosol Deposition of Nanostructured Coatings

Description

Nanomaterials exhibit unique properties that are substantially different from their bulk counterparts. These unique properties have gained recognition and application for various fields and products including sensors, displays, photovoltaics, and energy storage devices. Aerosol Deposition (AD) is a relatively new

Nanomaterials exhibit unique properties that are substantially different from their bulk counterparts. These unique properties have gained recognition and application for various fields and products including sensors, displays, photovoltaics, and energy storage devices. Aerosol Deposition (AD) is a relatively new method for depositing nanomaterials. AD utilizes a nozzle to accelerate the nanomaterial into a deposition chamber under near-vacuum conditions towards a substrate with which the nanomaterial collides and adheres. Traditional methods for designing nozzles at atmospheric conditions are not well suited for nozzle design for AD methods.

Computational Fluid Dynamics (CFD) software, ANSYS Fluent, is utilized to simulate two-phase flows consisting of a carrier gas (Helium) and silicon nanoparticles. The Cunningham Correction Factor is used to account for non-continuous effects at the relatively low pressures utilized in AD.

The nozzle, referred to herein as a boundary layer compensation (BLC) nozzle, comprises an area-ratio which is larger than traditionally designed nozzles to compensate for the thick boundary layer which forms within the viscosity-affected carrier gas flow. As a result, nanoparticles impact the substrate at velocities up to 300 times faster than the baseline nozzle.

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Date Created
2017

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Lateral Programmable Metallization Cells: Materials, Devices and Mechanisms

Description

Lateral programmable metallization cells (PMC) utilize the properties of electrodeposits grown over a solid electrolyte channel. Such devices have an active anode and an inert cathode separated by a long electrodeposit channel in a coplanar arrangement. The ability to transport

Lateral programmable metallization cells (PMC) utilize the properties of electrodeposits grown over a solid electrolyte channel. Such devices have an active anode and an inert cathode separated by a long electrodeposit channel in a coplanar arrangement. The ability to transport large amount of metallic mass across the channel makes these devices attractive for various More-Than-Moore applications. Existing literature lacks a comprehensive study of electrodeposit growth kinetics in lateral PMCs. Moreover, the morphology of electrodeposit growth in larger, planar devices is also not understood. Despite the variety of applications, lateral PMCs are not embraced by the semiconductor industry due to incompatible materials and high operating voltages needed for such devices. In this work, a numerical model based on the basic processes in PMCs – cation drift and redox reactions – is proposed, and the effect of various materials parameters on the electrodeposit growth kinetics is reported. The morphology of the electrodeposit growth and kinetics of the electrodeposition process are also studied in devices based on Ag-Ge30Se70 materials system. It was observed that the electrodeposition process mainly consists of two regimes of growth – cation drift limited regime and mixed regime. The electrodeposition starts in cation drift limited regime at low electric fields and transitions into mixed regime as the field increases. The onset of mixed regime can be controlled by applied voltage which also affects the morphology of electrodeposit growth. The numerical model was then used to successfully predict the device kinetics and onset of mixed regime. The problem of materials incompatibility with semiconductor manufacturing was solved by proposing a novel device structure. A bilayer structure using semiconductor foundry friendly materials was suggested as a candidate for solid electrolyte. The bilayer structure consists of a low resistivity oxide shunt layer on top of a high resistivity ion carrying oxide layer. Devices using Cu2O as the low resistivity shunt on top of Cu doped WO3 oxide were fabricated. The bilayer devices provided orders of magnitude improvement in device performance in the context of operating voltage and switching time. Electrical and materials characterization revealed the structure of bilayers and the mechanism of electrodeposition in these devices.

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Date Created
2020

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Spin-on Glass and LOR 3A Resist-based Planarization Technique for Neuromorphic CMOS Chips

Description

Most hardware today is based on von Neumann architecture separating memory from logic. Valuable processing time is lost in shuttling information back and forth between the two units, a problem called von Neumann bottleneck. As transistors are scaled further down,

Most hardware today is based on von Neumann architecture separating memory from logic. Valuable processing time is lost in shuttling information back and forth between the two units, a problem called von Neumann bottleneck. As transistors are scaled further down, this bottleneck will make it harder to deliver performance in computing power. Adding to this is the increasing complexity of artificial intelligence logic. Thus, there is a need for a faster and more efficient method of computing. Neuromorphic systems deliver this by emulating the massively parallel and fault-tolerant computing capabilities of the human brain where the action potential is triggered by multiple inputs at once (spatial) or an input that builds up over time (temporal). Highly scalable memristors are key in these systems- they can maintain their internal resistive state based on previous current/voltage values thus mimicking the way the strength of two synapses in the brain can vary. The brain-inspired algorithms are implemented by vector matrix multiplications (VMMs) to provide neuronal outputs. High-density conductive bridging random access memory (CBRAM) crossbar arrays (CBAs) can perform VMMs parallelly with ultra-low energy.This research explores a simple planarization technique that could be potentially extended to integrate front-end-of-line (FEOL) processing of complementary metal oxide semiconductor (CMOS) circuitry with back-end-of-line (BEOL) processing of CBRAM CBAs for one-transistor one-resistor (1T1R) Neuromorphic CMOS chips where the transistor is part of the CMOS circuitry and the CBRAM forms the resistor. It is a photoresist (PR) and spin-on glass (SOG) based planarization recipe to planarize CBRAM electrode patterns on a silicon substrate. In this research, however, the planarization is only applied to mechanical grade (MG) silicon wafers without any CMOS layers on them. The planarization achieved was of a very high order (few tens of nanometers). Additionally, the recipe is cost-effective, provides good quality films and simple as only two types of process technologies are involved- lithography and dry etching.
Subsequent processing would involve depositing the CBRAM layers onto the planarized electrodes to form the resistor. Finally, the entire process flow is to be replicated onto wafers with CMOS layers to form the 1T1R circuit.

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Date Created
2021