Matching Items (402)
Description
The end of the nineteenth century was an exhilarating and revolutionary era for the flute. This period is the Second Golden Age of the flute, when players and teachers associated with the Paris Conservatory developed what would be considered the birth of the modern flute school. In addition, the founding in 1871 of the Société Nationale de Musique by Camille Saint-Saëns (1835-1921) and Romain Bussine (1830-1899) made possible the promotion of contemporary French composers. The founding of the Société des Instruments à Vent by Paul Taffanel (1844-1908) in 1879 also invigorated a new era of chamber music for wind instruments. Within this groundbreaking environment, Mélanie Hélène Bonis (pen name Mel Bonis) entered the Paris Conservatory in 1876, under the tutelage of César Franck (1822-1890). Many flutists are dismayed by the scarcity of repertoire for the instrument in the Romantic and post-Romantic traditions; they make up for this absence by borrowing the violin sonatas of Gabriel Fauré (1845-1924) and Franck. The flute and piano works of Mel Bonis help to fill this void with music composed originally for flute. Bonis was a prolific composer with over 300 works to her credit, but her works for flute and piano have not been researched or professionally recorded in the United States before the present study. Although virtually unknown today in the American flute community, Bonis's music received much acclaim from her contemporaries and deserves a prominent place in the flutist's repertoire. After a brief biographical introduction, this document examines Mel Bonis's musical style and describes in detail her six works for flute and piano while also offering performance suggestions.
ContributorsDaum, Jenna Elyse (Author) / Buck, Elizabeth (Thesis advisor) / Holbrook, Amy (Committee member) / Micklich, Albie (Committee member) / Schuring, Martin (Committee member) / Norton, Kay (Committee member) / Arizona State University (Publisher)
Created2013
ContributorsMatthews, Eyona (Performer) / Yoo, Katie Jihye (Performer) / Roubison, Ryan (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-25
Description
ABSTRACT Electronics especially mobile electronics such as smart phones, tablet PCs, notebooks and digital cameras are undergoing rapid development nowadays and have thoroughly changed our lives. With the requirement of more transistors, higher power, smaller size, lighter weight and even bendability, thermal management of these devices became one of the key challenges. Compared to active heat management system, heat pipe, which is a passive fluidic system, is considered promising to solve this problem. However, traditional heat pipes have size, weight and capillary limitation. Thus new type of heat pipe with smaller size, lighter weight and higher capillary pressure is needed. Nanofiber has been proved with superior properties and has been applied in multiple areas. This study discussed the possibility of applying nanofiber in heat pipe as new wick structure. In this study, a needleless electrospinning device with high productivity rate was built onsite to systematically investigate the effect of processing parameters on fiber properties as well as to generate nanofiber mat to evaluate its capability in electronics cooling. Polyethylene oxide (PEO) and Polyvinyl Alcohol (PVA) nanofibers were generated. Tensiometer was used for wettability measurement. The results show that independent parameters including spinneret type, working distance, solution concentration and polymer type are strongly correlated with fiber morphology compared to other parameters. The results also show that the fabricated nanofiber mat has high capillary pressure.
ContributorsSun, Tianwei (Author) / Jiang, Hanqing (Thesis advisor) / Yu, Hongyu (Committee member) / Chen, Kangping (Committee member) / Arizona State University (Publisher)
Created2014
ContributorsHoeckley, Stephanie (Performer) / Lee, Juhyun (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-24
Description
In this work, a highly sensitive strain sensing technique is developed to realize in-plane strain mapping for microelectronic packages or emerging flexible or foldable devices, where mechanical or thermal strain is a major concern that could affect the performance of the working devices or even lead to the failure of the devices. Therefore strain sensing techniques to create a contour of the strain distribution is desired.
The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.
The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.
In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.
The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.
In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Poon, Poh Chieh Benny (Committee member) / Jiang, Hanqing (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
ContributorsMcClain, Katelyn (Performer) / Buringrud, Deanna (Contributor) / Lee, Juhyun (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-31
Description
This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20µm - 200µm, fine traces with varying widths of 3µm - 30µm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show “smart” control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry.
ContributorsGanesan, Kousik (Author) / Tasooji, Amaneh (Thesis advisor) / Manepalli, Rahul (Committee member) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2018
ContributorsHur, Jiyoun (Performer) / Lee, Juhyun (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-01
ContributorsZaleski, Kimberly (Contributor) / Kazarian, Trevor (Performer) / Ryan, Russell (Performer) / IN2ATIVE (Performer) / ASU Library. Music Library (Publisher)
Created2018-09-28
Description
For a (N+1)-bus power system, possibly 2N solutions exists. One of these solutions
is known as the high-voltage (HV) solution or operable solution. The rest of the solutions
are the low-voltage (LV), or large-angle, solutions.
In this report, a recently developed non-iterative algorithm for solving the power-
flow (PF) problem using the holomorphic embedding (HE) method is shown as
being capable of finding the HV solution, while avoiding converging to LV solutions
nearby which is a drawback to all other iterative solutions. The HE method provides a
novel non-iterative procedure to solve the PF problems by eliminating the
non-convergence and initial-estimate dependency issues appeared in the traditional
iterative methods. The detailed implementation of the HE method is discussed in the
report.
While published work focuses mainly on finding the HV PF solution, modified
holomorphically embedded formulations are proposed in this report to find the
LV/large-angle solutions of the PF problem. It is theoretically proven that the proposed
method is guaranteed to find a total number of 2N solutions to the PF problem
and if no solution exists, the algorithm is guaranteed to indicate such by the oscillations
in the maximal analytic continuation of the coefficients of the voltage power series
obtained.
After presenting the derivation of the LV/large-angle formulations for both PQ
and PV buses, numerical tests on the five-, seven- and 14-bus systems are conducted
to find all the solutions of the system of nonlinear PF equations for those systems using
the proposed HE method.
After completing the derivation to find all the PF solutions using the HE method, it
is shown that the proposed HE method can be used to find only the of interest PF solutions
(i.e. type-1 PF solutions with one positive real-part eigenvalue in the Jacobian
matrix), with a proper algorithm developed. The closet unstable equilibrium point
(UEP), one of the type-1 UEP’s, can be obtained by the proposed HE method with
limited dynamic models included.
The numerical performance as well as the robustness of the proposed HE method is
investigated and presented by implementing the algorithm on the problematic cases and
large-scale power system.
is known as the high-voltage (HV) solution or operable solution. The rest of the solutions
are the low-voltage (LV), or large-angle, solutions.
In this report, a recently developed non-iterative algorithm for solving the power-
flow (PF) problem using the holomorphic embedding (HE) method is shown as
being capable of finding the HV solution, while avoiding converging to LV solutions
nearby which is a drawback to all other iterative solutions. The HE method provides a
novel non-iterative procedure to solve the PF problems by eliminating the
non-convergence and initial-estimate dependency issues appeared in the traditional
iterative methods. The detailed implementation of the HE method is discussed in the
report.
While published work focuses mainly on finding the HV PF solution, modified
holomorphically embedded formulations are proposed in this report to find the
LV/large-angle solutions of the PF problem. It is theoretically proven that the proposed
method is guaranteed to find a total number of 2N solutions to the PF problem
and if no solution exists, the algorithm is guaranteed to indicate such by the oscillations
in the maximal analytic continuation of the coefficients of the voltage power series
obtained.
After presenting the derivation of the LV/large-angle formulations for both PQ
and PV buses, numerical tests on the five-, seven- and 14-bus systems are conducted
to find all the solutions of the system of nonlinear PF equations for those systems using
the proposed HE method.
After completing the derivation to find all the PF solutions using the HE method, it
is shown that the proposed HE method can be used to find only the of interest PF solutions
(i.e. type-1 PF solutions with one positive real-part eigenvalue in the Jacobian
matrix), with a proper algorithm developed. The closet unstable equilibrium point
(UEP), one of the type-1 UEP’s, can be obtained by the proposed HE method with
limited dynamic models included.
The numerical performance as well as the robustness of the proposed HE method is
investigated and presented by implementing the algorithm on the problematic cases and
large-scale power system.
ContributorsMine, Yō (Author) / Tylavsky, Daniel (Thesis advisor) / Armbruster, Dieter (Committee member) / Holbert, Keith E. (Committee member) / Sankar, Lalitha (Committee member) / Vittal, Vijay (Committee member) / Undrill, John (Committee member) / Arizona State University (Publisher)
Created2015