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- Genre: Doctoral Dissertation
Description
Inductors are fundamental components that do not scale well. Their physical limitations to scalability along with their inherent losses make them the main obstacle in achieving monolithic system-on-chip platform (SoCP). For past decades researchers focused on integrating magnetic materials into on-chip inductors in the quest of achieving high inductance density and quality factor (QF). The state of the art on-chip inductor is made of an enclosed magnetic thin-film around the current carrying wire for maximum flux amplification. Though the integration of magnetic materials results in enhanced inductor characteristics, this approach has its own challenges and limitations especially in power applications. The current-induced magnetic field (HDC) drives the magnetic film into its saturation state. At saturation, inductance and QF drop to that of air-core inductors, eliminating the benefits of integrating magnetic materials. Increasing the current carrying capability without substantially sacrificing benefits brought on by the magnetic material is an open challenge in power applications. Researchers continue to address this challenge along with the continuous improvement in inductance and QF for RF and power applications.
In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
ContributorsKhdour, Mahmoud (Author) / Yu, Hongbin (Thesis advisor) / Pan, George (Committee member) / Goryll, Michael (Committee member) / Bearat, Hamdallah (Committee member) / Arizona State University (Publisher)
Created2014
Description
InAs/InAsSb type-II superlattices (T2SLs) can be considered as potential alternatives for conventional HgCdTe photodetectors due to improved uniformity, lower manufacturing costs with larger substrates, and possibly better device performance. This dissertation presents a comprehensive study on the structural, optical and electrical properties of InAs/InAsSb T2SLs grown by Molecular Beam Epitaxy.
The effects of different growth conditions on the structural quality were thoroughly investigated. Lattice-matched condition was successfully achieved and material of exceptional quality was demonstrated.
After growth optimization had been achieved, structural defects could hardly be detected, so different characterization techniques, including etch-pit-density (EPD) measurements, cathodoluminescence (CL) imaging and X-ray topography (XRT), were explored, in attempting to gain better knowledge of the sparsely distributed defects. EPD revealed the distribution of dislocation-associated pits across the wafer. Unfortunately, the lack of contrast in images obtained by CL imaging and XRT indicated their inability to provide any quantitative information about defect density in these InAs/InAsSb T2SLs.
The nBn photodetectors based on mid-wave infrared (MWIR) and long-wave infrared (LWIR) InAs/InAsSb T2SLs were fabricated. The significant difference in Ga composition in the barrier layer coupled with different dark current behavior, suggested the possibility of different types of band alignment between the barrier layers and the absorbers. A positive charge density of 1.8 × 1017/cm3 in the barrier of MWIR nBn photodetector, as determined by electron holography, confirmed the presence of a potential well in its valence band, thus identifying type-II alignment. In contrast, the LWIR nBn photodetector was shown to have type-I alignment because no sign of positive charge was detected in its barrier.
Capacitance-voltage measurements were performed to investigate the temperature dependence of carrier densities in a metal-oxide-semiconductor (MOS) structure based on MWIR InAs/InAsSb T2SLs, and a nBn structure based on LWIR InAs/InAsSb T2SLs. No carrier freeze-out was observed in either sample, indicating very shallow donor levels. The decrease in carrier density when temperature increased was attributed to the increased density of holes that had been thermally excited from localized states near the oxide/semiconductor interface in the MOS sample. No deep-level traps were revealed in deep-level transient spectroscopy temperature scans.
The effects of different growth conditions on the structural quality were thoroughly investigated. Lattice-matched condition was successfully achieved and material of exceptional quality was demonstrated.
After growth optimization had been achieved, structural defects could hardly be detected, so different characterization techniques, including etch-pit-density (EPD) measurements, cathodoluminescence (CL) imaging and X-ray topography (XRT), were explored, in attempting to gain better knowledge of the sparsely distributed defects. EPD revealed the distribution of dislocation-associated pits across the wafer. Unfortunately, the lack of contrast in images obtained by CL imaging and XRT indicated their inability to provide any quantitative information about defect density in these InAs/InAsSb T2SLs.
The nBn photodetectors based on mid-wave infrared (MWIR) and long-wave infrared (LWIR) InAs/InAsSb T2SLs were fabricated. The significant difference in Ga composition in the barrier layer coupled with different dark current behavior, suggested the possibility of different types of band alignment between the barrier layers and the absorbers. A positive charge density of 1.8 × 1017/cm3 in the barrier of MWIR nBn photodetector, as determined by electron holography, confirmed the presence of a potential well in its valence band, thus identifying type-II alignment. In contrast, the LWIR nBn photodetector was shown to have type-I alignment because no sign of positive charge was detected in its barrier.
Capacitance-voltage measurements were performed to investigate the temperature dependence of carrier densities in a metal-oxide-semiconductor (MOS) structure based on MWIR InAs/InAsSb T2SLs, and a nBn structure based on LWIR InAs/InAsSb T2SLs. No carrier freeze-out was observed in either sample, indicating very shallow donor levels. The decrease in carrier density when temperature increased was attributed to the increased density of holes that had been thermally excited from localized states near the oxide/semiconductor interface in the MOS sample. No deep-level traps were revealed in deep-level transient spectroscopy temperature scans.
ContributorsShen, Xiaomeng (Author) / Zhang, Yong-Hang (Thesis advisor) / Smith, David J. (Thesis advisor) / Alford, Terry (Committee member) / Goryll, Michael (Committee member) / Mccartney, Martha R (Committee member) / Arizona State University (Publisher)
Created2015
Description
Interdigitated back contact (IBC) solar cells have achieved the highest single junction silicon wafer-based solar cell power conversion efficiencies reported to date. This thesis is about the fabrication of a high-efficiency silicon heterojunction IBC solar cell for potential use as the bottom cell for a 3-terminal lattice-matched dilute-nitride Ga (In)NP(As)/Si monolithic tandem solar cell. An effective fabrication process has been developed and the process challenges related to open circuit voltage (Voc), series resistance (Rs), and fill factor (FF) are experimentally analyzed. While wet etching, the sample lost the initial passivation, and by changing the etchant solution and passivation process, the voltage at maximum power recovered to an initial value of over 710 mV before metallization. The factors reducing the series resistance loss in IBC cells were also studied. One of these factors was the Indium Tin Oxide (ITO) sputtering parameters, which impact the conductivity of the ITO layer and transport across the a-Si:H/ITO interface. For the standard recipe, the chamber pressure was 3.5 mTorr with no oxygen partial pressure, and the thickness of the ITO layer in contact with the a-Si:H layers, was optimized to 150 nm. The patterning method for the metal contacts and final annealing also change the contact resistance of the base and emitter stack layers. The final annealing step is necessary to recover the sputtering damage; however, the higher the annealing time the higher the final IBC series resistance. The best efficiency achieved was 19.3% (Jsc = 37 mA/cm2, Voc = 691 mV, FF = 71.7%) on 200 µm thick 1-15 Ω-cm n-type CZ C-Si with a designated area of 4 cm2.
ContributorsMoeini Rizi, Mansoure (Author) / Goodnick, Stephen (Thesis advisor) / Honsberg, Christina (Committee member) / Goryll, Michael (Committee member) / Smith, David (Committee member) / Bowden, Stuart (Committee member) / Arizona State University (Publisher)
Created2022