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Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
Description
This dissertation addresses challenges pertaining to multi-junction (MJ) solar cells from material development to device design and characterization. Firstly, among the various methods to improve the energy conversion efficiency of MJ solar cells using, a novel approach proposed recently is to use II-VI (MgZnCd)(SeTe) and III-V (AlGaIn)(AsSb) semiconductors lattice-matched on GaSb or InAs substrates for current-matched subcells with minimal defect densities. CdSe/CdTe superlattices are proposed as a potential candidate for a subcell in the MJ solar cell designs using this material system, and therefore the material properties of the superlattices are studied. The high structural qualities of the superlattices are obtained from high resolution X-ray diffraction measurements and cross-sectional transmission electron microscopy images. The effective bandgap energies of the superlattices obtained from the photoluminescence (PL) measurements vary with the layer thicknesses, and are smaller than the bandgap energies of either the constituent material. Furthermore, The PL peak position measured at the steady state exhibits a blue shift that increases with the excess carrier concentration. These results confirm a strong type-II band edge alignment between CdSe and CdTe. The valence band offset between unstrained CdSe and CdTe is determined as 0.63 eV±0.06 eV by fitting the measured PL peak positions using the Kronig-Penney model. The blue shift in PL peak position is found to be primarily caused by the band bending effect based on self-consistent solutions of the Schrödinger and Poisson equations. Secondly, the design of the contact grid layout is studied to maximize the power output and energy conversion efficiency for concentrator solar cells. Because the conventional minimum power loss method used for the contact design is not accurate in determining the series resistance loss, a method of using a distributed series resistance model to maximize the power output is proposed for the contact design. It is found that the junction recombination loss in addition to the series resistance loss and shadowing loss can significantly affect the contact layout. The optimal finger spacing and maximum efficiency calculated by the two methods are close, and the differences are dependent on the series resistance and saturation currents of solar cells. Lastly, the accurate measurements of external quantum efficiency (EQE) are important for the design and development of MJ solar cells. However, the electrical and optical couplings between the subcells have caused EQE measurement artifacts. In order to interpret the measurement artifacts, DC and small signal models are built for the bias condition and the scan of chopped monochromatic light in the EQE measurements. Characterization methods are developed for the device parameters used in the models. The EQE measurement artifacts are found to be caused by the shunt and luminescence coupling effects, and can be minimized using proper voltage and light biases. Novel measurement methods using a pulse voltage bias or a pulse light bias are invented to eliminate the EQE measurement artifacts. These measurement methods are nondestructive and easy to implement. The pulse voltage bias or pulse light bias is superimposed on the conventional DC voltage and light biases, in order to control the operating points of the subcells and counterbalance the effects of shunt and luminescence coupling. The methods are demonstrated for the first time to effectively eliminate the measurement artifacts.
ContributorsLi, Jingjing (Author) / Zhang, Yong-Hang (Thesis advisor) / Tao, Meng (Committee member) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
Potential-Induced Degradation (PID) is an extremely serious photovoltaic (PV) durability issue significantly observed in crystalline silicon PV modules due to its rapid power degradation, particularly when compared to other PV degradation modes. The focus of this dissertation is to understand PID mechanisms and to develop PID-free cells and modules. PID-affected modules have been claimed to be fully recovered by high temperature and reverse potential treatments. However, the results obtained in this work indicate that the near-full recovery of efficiency can be achieved only at high irradiance conditions, but the full recovery of efficiency at low irradiance levels, of shunt resistance, and of quantum efficiency (QE) at short wavelengths could not be achieved. The QE loss observed at short wavelengths was modeled by changing the front surface recombination velocity. The QE scaling error due to a measurement on a PID shunted cell was addressed by developing a very low input impedance accessory applicable to an existing QE system. The impacts of silicon nitride (SiNx) anti-reflection coating (ARC) refractive index (RI) and emitter sheet resistance on PID are presented. Low RI ARC cells (1.87) were observed to be PID-susceptible whereas high RI ARC cells (2.05) were determined to be PID-resistant using a method employing high dose corona charging followed by time-resolved measurement of surface voltage. It has been demonstrated that the PID could be prevented by deploying an emitter having a low sheet resistance (~ 60 /sq) even if a PID-susceptible ARC is used in a cell. Secondary ion mass spectroscopy (SIMS) results suggest that a high phosphorous emitter layer hinders sodium transport, which is responsible for the PID. Cells can be screened for PID susceptibility by illuminated lock-in thermography (ILIT) during the cell fabrication process, and the sample structure for this can advantageously be simplified as long as the sample has the SiNx ARC and an aluminum back surface field. Finally, this dissertation presents a prospective method for eliminating or minimizing the PID issue either in the factory during manufacturing or in the field after system installation. The method uses commercially available, thin, and flexible Corning® Willow® Glass sheets or strips on the PV module glass superstrates, disrupting the current leakage path from the cells to the grounded frame.
ContributorsOh, Jaewon (Author) / Bowden, Stuart (Thesis advisor) / Tamizhmani, Govindasamy (Thesis advisor) / Honsberg, Christiana (Committee member) / Hacke, Peter (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2016