Matching Items (18)
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- All Subjects: Semiconductors
- Creators: Vasileska, Dragica
- Creators: Zhang, Yong-Hang
- Creators: Simonson, Mark
Description
From 2D planar MOSFET to 3D FinFET, the geometry of semiconductor devices is getting more and more complex. Correspondingly, the number of mesh grid points increases largely to maintain the accuracy of carrier transport and heat transfer simulations. By substituting the conventional uniform mesh with non-uniform mesh, one can reduce the number of grid points. However, the problem of how to solve governing equations on non-uniform mesh is then imposed to the numerical solver. Moreover, if a device simulator is integrated into a multi-scale simulator, the problem size will be further increased. Consequently, there exist two challenges for the current numerical solver. One is to increase the functionality to accommodate non-uniform mesh. The other is to solve governing physical equations fast and accurately on a large number of mesh grid points.
This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
ContributorsGuo, Xinchen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Ferry, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
There has been recent interest in demonstrating solar cells which approach the detailed-balance or thermodynamic efficiency limit in order to establish a model system for which mass-produced solar cells can be designed. Polycrystalline CdS/CdTe heterostructures are currently one of many competing solar cell material systems. Despite being polycrystalline, efficiencies up to 21 % have been demonstrated by the company First Solar. However, this efficiency is still far from the detailed-balance limit of 32.1 % for CdTe. This work explores the use of monocrystalline CdTe/MgCdTe and ZnTe/CdTe/MgCdTe double heterostructures (DHs) grown on (001) InSb substrates by molecular beam epitaxy (MBE) for photovoltaic applications.
Undoped CdTe/MgCdTe DHs are first grown in order to determine the material quality of the CdTe epilayer and to optimize the growth conditions. DH samples show strong photoluminescence with over double the intensity as that of a GaAs/AlGaAs DH with an identical layer structure. Time-resolved photoluminescence of the CdTe/MgCdTe DH gives a carrier lifetime of up to 179 ns for a 2 µm thick CdTe layer, which is more than one order of magnitude longer than that of polycrystalline CdTe films. MgCdTe barrier layers are found to be effective at confining photogenerated carriers and have a relatively low interface recombination velocity of 461 cm/s. The optimal growth temperature and Cd/Te flux ratio is determined to be 265 °C and 1.5, respectively.
Monocrystalline ZnTe/CdTe/MgCdTe P-n-N DH solar cells are designed, grown, processed into solar cell devices, and characterized. A maximum efficiency of 6.11 % is demonstrated for samples without an anti-reflection coating. The low efficiency is mainly due to the low open-circuit voltage (Voc), which is attributed to high dark current caused by interface recombination at the ZnTe/CdTe interface. Low-temperature measurements show a linear increase in Voc with decreasing temperature down to 77 K, which suggests that the room-temperature operation is limited by non-radiative recombination. An open-circuit voltage of 1.22 V and an efficiency of 8.46 % is demonstrated at 77 K. It is expected that a coherently strained MgCdTe/CdTe/MgCdTe DH solar cell design will produce higher efficiency and Voc compared to the ZnTe/CdTe/MgCdTe design with relaxed ZnTe layer.
Undoped CdTe/MgCdTe DHs are first grown in order to determine the material quality of the CdTe epilayer and to optimize the growth conditions. DH samples show strong photoluminescence with over double the intensity as that of a GaAs/AlGaAs DH with an identical layer structure. Time-resolved photoluminescence of the CdTe/MgCdTe DH gives a carrier lifetime of up to 179 ns for a 2 µm thick CdTe layer, which is more than one order of magnitude longer than that of polycrystalline CdTe films. MgCdTe barrier layers are found to be effective at confining photogenerated carriers and have a relatively low interface recombination velocity of 461 cm/s. The optimal growth temperature and Cd/Te flux ratio is determined to be 265 °C and 1.5, respectively.
Monocrystalline ZnTe/CdTe/MgCdTe P-n-N DH solar cells are designed, grown, processed into solar cell devices, and characterized. A maximum efficiency of 6.11 % is demonstrated for samples without an anti-reflection coating. The low efficiency is mainly due to the low open-circuit voltage (Voc), which is attributed to high dark current caused by interface recombination at the ZnTe/CdTe interface. Low-temperature measurements show a linear increase in Voc with decreasing temperature down to 77 K, which suggests that the room-temperature operation is limited by non-radiative recombination. An open-circuit voltage of 1.22 V and an efficiency of 8.46 % is demonstrated at 77 K. It is expected that a coherently strained MgCdTe/CdTe/MgCdTe DH solar cell design will produce higher efficiency and Voc compared to the ZnTe/CdTe/MgCdTe design with relaxed ZnTe layer.
ContributorsDiNezza, Michael John (Author) / Zhang, Yong-Hang (Thesis advisor) / Johnson, Shane (Committee member) / Tao, Meng (Committee member) / Holman, Zachary (Committee member) / Arizona State University (Publisher)
Created2014
Description
In semiconductor physics, many properties or phenomena of materials can be brought to light through certain changes in the materials. Having a tool to define new material properties so as to highlight certain phenomena greatly increases the ability to understand that phenomena. The generalized Monte Carlo tool allows the user to do that by keeping every parameter used to define a material, within the non-parabolic band approximation, a variable in the control of the user. A material is defined by defining its valleys, energies, valley effective masses and their directions. The types of scattering to be included can also be chosen. The non-parabolic band structure model is used. With the deployment of the generalized Monte Carlo tool onto www.nanoHUB.org the tool will be available to users around the world. This makes it a very useful educational tool that can be incorporated into curriculums. The tool is integrated with Rappture, to allow user-friendly access of the tool. The user can freely define a material in an easy systematic way without having to worry about the coding involved. The output results are automatically graphed and since the code incorporates an analytic band structure model, it is relatively fast. The versatility of the tool has been investigated and has produced results closely matching the experimental values for some common materials. The tool has been uploaded onto www.nanoHUB.org by integrating it with the Rappture interface. By using Rappture as the user interface, one can easily make changes to the current parameter sets to obtain even more accurate results.
ContributorsHathwar, Raghuraj (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Saraniti, Marco (Committee member) / Arizona State University (Publisher)
Created2011
Description
A dual chamber molecular beam epitaxy (MBE) system was rebuilt for the growth of 6.1 Angstrom II-VI and III-V compound semiconductor materials that are to be used in novel optoelectronic devices that take advantage of the nearly continuous bandgap availability between 0 eV and 3.4 eV. These devices include multijunction solar cells and multicolor detectors. The MBE system upgrade involved the conversion of a former III-V chamber for II-VI growth. This required intensive cleaning of the chamber and components to prevent contamination. Special features including valved II-VI sources and the addition of a cold trap allowed for the full system to be baked to 200 degrees Celsius to improve vacuum conditions and reduce background impurity concentrations in epilayers. After the conversion, the system was carefully calibrated and optimized for the growth of ZnSe and ZnTe on GaAs (001) substrates. Material quality was assessed using X-ray diffraction rocking curves. ZnSe layers displayed a trend of improving quality with decreasing growth temperature reaching a minimum full-width half-maximum (FWHM) of 113 arcsec at 278 degrees Celsius. ZnTe epilayer quality increased with growth temperature under Zn rich conditions attaining a FWHM of 84 arcsec at 440 degrees Celsius. RHEED oscillations were successfully observed and used to obtain growth rate in situ for varying flux and temperature levels. For a fixed flux ratio, growth rate decreased with growth temperature as the desorption rate increased. A directly proportional dependence of growth rate on Te flux was observed for Zn rich growth. Furthermore, a method for determining the flux ratio necessary for attaining the stoichiometric condition was demonstrated.
ContributorsDettlaff, W. Hank G (Author) / Zhang, Yong-Hang (Thesis advisor) / Vasileska, Dragica (Committee member) / Johnson, Shane (Committee member) / Arizona State University (Publisher)
Created2012
Description
This dissertation addresses challenges pertaining to multi-junction (MJ) solar cells from material development to device design and characterization. Firstly, among the various methods to improve the energy conversion efficiency of MJ solar cells using, a novel approach proposed recently is to use II-VI (MgZnCd)(SeTe) and III-V (AlGaIn)(AsSb) semiconductors lattice-matched on GaSb or InAs substrates for current-matched subcells with minimal defect densities. CdSe/CdTe superlattices are proposed as a potential candidate for a subcell in the MJ solar cell designs using this material system, and therefore the material properties of the superlattices are studied. The high structural qualities of the superlattices are obtained from high resolution X-ray diffraction measurements and cross-sectional transmission electron microscopy images. The effective bandgap energies of the superlattices obtained from the photoluminescence (PL) measurements vary with the layer thicknesses, and are smaller than the bandgap energies of either the constituent material. Furthermore, The PL peak position measured at the steady state exhibits a blue shift that increases with the excess carrier concentration. These results confirm a strong type-II band edge alignment between CdSe and CdTe. The valence band offset between unstrained CdSe and CdTe is determined as 0.63 eV±0.06 eV by fitting the measured PL peak positions using the Kronig-Penney model. The blue shift in PL peak position is found to be primarily caused by the band bending effect based on self-consistent solutions of the Schrödinger and Poisson equations. Secondly, the design of the contact grid layout is studied to maximize the power output and energy conversion efficiency for concentrator solar cells. Because the conventional minimum power loss method used for the contact design is not accurate in determining the series resistance loss, a method of using a distributed series resistance model to maximize the power output is proposed for the contact design. It is found that the junction recombination loss in addition to the series resistance loss and shadowing loss can significantly affect the contact layout. The optimal finger spacing and maximum efficiency calculated by the two methods are close, and the differences are dependent on the series resistance and saturation currents of solar cells. Lastly, the accurate measurements of external quantum efficiency (EQE) are important for the design and development of MJ solar cells. However, the electrical and optical couplings between the subcells have caused EQE measurement artifacts. In order to interpret the measurement artifacts, DC and small signal models are built for the bias condition and the scan of chopped monochromatic light in the EQE measurements. Characterization methods are developed for the device parameters used in the models. The EQE measurement artifacts are found to be caused by the shunt and luminescence coupling effects, and can be minimized using proper voltage and light biases. Novel measurement methods using a pulse voltage bias or a pulse light bias are invented to eliminate the EQE measurement artifacts. These measurement methods are nondestructive and easy to implement. The pulse voltage bias or pulse light bias is superimposed on the conventional DC voltage and light biases, in order to control the operating points of the subcells and counterbalance the effects of shunt and luminescence coupling. The methods are demonstrated for the first time to effectively eliminate the measurement artifacts.
ContributorsLi, Jingjing (Author) / Zhang, Yong-Hang (Thesis advisor) / Tao, Meng (Committee member) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis mainly focuses on the study of quantum efficiency (QE) and its measurement, especially for nanowires (NWs). First, a brief introduction of nano-technology and nanowire is given to describe my initial research interest. Next various fundamental kinds of recombination mechanisms are described; both for radiative and non-radiative processes. This is an introduction for defining the internal quantum efficiency (IQE). A relative IQE measurement method is shown following that. Then it comes to the major part of the thesis discussing a procedure of quantum efficiency measurement using photoluminescence (PL) method and an integrating sphere, which has not been much applied to nanowires (NWs). In fact this is a convenient and useful approach for evaluating the quality of NWs since it considers not only the PL emission but also the absorption of NWs. The process is well illustrated and performed with both wavelength-dependent and power-dependent measurements. The measured PLQE is in the range of 0.3% ~ 5.4%. During the measurement, a phenomenon called photodegradation is observed and examined by a set of power-dependence measurements. This effect can be a factor for underestimating the PLQE and a procedure is introduced during the sample preparation process which managed to reduce this effect for some degree.
ContributorsChen, Dongzi (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
The purpose of this thesis was to design a market entrance strategy for Company X to enter the microcontroller (MCU) market within the Internet of Things (IoT). The five IoT segments are automotive; medical; retail; industrial; and military, aerospace, and government. To reach a final decision, we will research the markets, analyze make versus buy scenarios, and deliver a financial analysis on the chosen strategy. Based on the potential financial benefits and compatibility with Company X's current business model, we recommend that Company X enter the automotive segment through mergers & acquisitions (M&A). After analyzing the supply chain structure of the automotive IoT, we advise Company X to acquire Freescale Semiconductor for $46.98 per share.
ContributorsBradley, Rachel (Co-author) / Fankhauser, Elisa (Co-author) / McCoach, Robert (Co-author) / Zheng, Weilin (Co-author) / Simonson, Mark (Thesis director) / Hertzel, Mike (Committee member) / Barrett, The Honors College (Contributor) / Department of Finance (Contributor) / Department of Supply Chain Management (Contributor) / School of Accountancy (Contributor) / School of International Letters and Cultures (Contributor) / WPC Graduate Programs (Contributor)
Created2015-05
Description
Company X is one of the world's largest semiconductor companies in the world, having a current market capitalization of 177.44 Billion USD, an enterprise value of 173.6 Billion USD, and generated 52.7 billion USD in revenue in fiscal year 2013. Recently, Company X has been looking to expand its Foundry business. The Foundry business in the semiconductor business is the actual process of making the chips. This process can be approached in several different ways by companies who need their chips built. A company, like TSMC, can be considered a pure-play company and only makes chips for other companies. A fabless company, like Apple, creates its own chip design and then allows another company to build them. It also uses other chip designs for its products, but outsources the building to another company. Lastly, the integrated device manufacturing companies like Samsung or Company X both design and build the chip. The foundry industry is a rather novel market for Company X because it owns less than 1 percent of the market. However, the industry itself is rather large, generating a total of 40 billion dollars in revenue annually, with expectations to have increasing year over year growth into the foreseeable future. The industry is fairly concentrated with TSMC being the top competitor, owning roughly 50 percent of the market with Samsung and Global Foundries lagging behind as notable competitors. It is a young industry and there is potential opportunity for companies that want to get into the business. For Company X, it is not only another market to get into, but also an added business segment to supplant their business segments that are forecasted to do poorly in the near future. This thesis will analyze the financial opportunity for Company X in the foundry space. Our final product is a series of P&L's which illustrate our findings. The results of our analysis were presented and defended in front of a panel of Company X managers and executives.
ContributorsJones, Trevor (Author) / Matiski, Matthew (Co-author) / Green, Alex (Co-author) / Simonson, Mark (Thesis director) / Hertzel, Michael (Committee member) / Department of Finance (Contributor) / W. P. Carey School of Business (Contributor) / Barrett, The Honors College (Contributor)
Created2015-05
Description
Our thesis project aims to evaluate a major semiconductor company's (The Company) substrate supplier strategy in order to find the ideal number of suppliers that minimizes fixed cost and supplier power. With The Company spending roughly $2.2 billion annually on substrates, supplier strategy has a significant impact on their costs. As a general rule in micro processing, the circuitry of the processor becomes twice as dense every two years. The substrate, being the pathway through which the process or with the motherboard, must become more advanced as well, although the technology does not grow at nearly the same speed. Leading the way in their industry, The Company is at the forefront of technology and produces the world's most advanced processing units. The suppliers The Company purchases from must be innovators in their own respective fields in order to be capable of handling such "bleeding-edge" technology; this requires a supplier to make a commitment to continuously work towards meeting The Company's constantly changing technological requirements. The ultimate goal of this project is to determine the ideal number of substrate suppliers that balances the effects of production costs and buying power to give the company the best overall purchase price.
ContributorsWright, Brian (Author) / Hertzel, Michael (Thesis director) / Simonson, Mark (Committee member) / Shirts, John (Committee member) / Barrett, The Honors College (Contributor)
Created2012-05
Description
We gathered and analyzed key data from a wide-range of competitors in the foundry, fabless, and Integrated design manufacturing business. After detecting a downward trend in the return of invested capital (ROIC) and higher capital intensity of Company X, we searched for alternatives to turn this around. We conclude that, to decrease the net PPE of Company X, a sale-leaseback transaction would help Company X reduce their balance sheet and provided financing to advance their manufacturing capabilities.
ContributorsBhat, Arjun Khandige (Co-author) / Brock, Ethan (Co-author) / Gamperl, Max (Co-author) / Gupta, Viraj (Co-author) / Macha, Sanketh (Co-author) / Simonson, Mark (Thesis director) / Duran, Juan Carlos (Committee member) / Department of Finance (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05