Matching Items (20)
Filtering by
- All Subjects: Semiconductors
- All Subjects: Monte Carlo method
- Creators: Vasileska, Dragica
- Creators: Zhang, Yong-Hang
Description
The goal of this research work is to develop a particle-based device simulator for modeling strained silicon devices. Two separate modules had to be developed for that purpose: A generic bulk Monte Carlo simulation code which in the long-time limit solves the Boltzmann transport equation for electrons; and an extension to this code that solves for the bulk properties of strained silicon. One scattering table is needed for conventional silicon, whereas, because of the strain breaking the symmetry of the system, three scattering tables are needed for modeling strained silicon material. Simulation results for the average drift velocity and the average electron energy are in close agreement with published data. A Monte Carlo device simulation tool has also been employed to integrate the effects of self-heating into device simulation for Silicon on Insulator devices. The effects of different types of materials for buried oxide layers have been studied. Sapphire, Aluminum Nitride (AlN), Silicon dioxide (SiO2) and Diamond have been used as target materials of interest in the analysis and the effects of varying insulator layer thickness have also been investigated. It was observed that although AlN exhibits the best isothermal behavior, diamond is the best choice when thermal effects are accounted for.
ContributorsQazi, Suleman (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Tao, Meng (Committee member) / Arizona State University (Publisher)
Created2013
Description
From 2D planar MOSFET to 3D FinFET, the geometry of semiconductor devices is getting more and more complex. Correspondingly, the number of mesh grid points increases largely to maintain the accuracy of carrier transport and heat transfer simulations. By substituting the conventional uniform mesh with non-uniform mesh, one can reduce the number of grid points. However, the problem of how to solve governing equations on non-uniform mesh is then imposed to the numerical solver. Moreover, if a device simulator is integrated into a multi-scale simulator, the problem size will be further increased. Consequently, there exist two challenges for the current numerical solver. One is to increase the functionality to accommodate non-uniform mesh. The other is to solve governing physical equations fast and accurately on a large number of mesh grid points.
This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
ContributorsGuo, Xinchen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Ferry, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
There has been recent interest in demonstrating solar cells which approach the detailed-balance or thermodynamic efficiency limit in order to establish a model system for which mass-produced solar cells can be designed. Polycrystalline CdS/CdTe heterostructures are currently one of many competing solar cell material systems. Despite being polycrystalline, efficiencies up to 21 % have been demonstrated by the company First Solar. However, this efficiency is still far from the detailed-balance limit of 32.1 % for CdTe. This work explores the use of monocrystalline CdTe/MgCdTe and ZnTe/CdTe/MgCdTe double heterostructures (DHs) grown on (001) InSb substrates by molecular beam epitaxy (MBE) for photovoltaic applications.
Undoped CdTe/MgCdTe DHs are first grown in order to determine the material quality of the CdTe epilayer and to optimize the growth conditions. DH samples show strong photoluminescence with over double the intensity as that of a GaAs/AlGaAs DH with an identical layer structure. Time-resolved photoluminescence of the CdTe/MgCdTe DH gives a carrier lifetime of up to 179 ns for a 2 µm thick CdTe layer, which is more than one order of magnitude longer than that of polycrystalline CdTe films. MgCdTe barrier layers are found to be effective at confining photogenerated carriers and have a relatively low interface recombination velocity of 461 cm/s. The optimal growth temperature and Cd/Te flux ratio is determined to be 265 °C and 1.5, respectively.
Monocrystalline ZnTe/CdTe/MgCdTe P-n-N DH solar cells are designed, grown, processed into solar cell devices, and characterized. A maximum efficiency of 6.11 % is demonstrated for samples without an anti-reflection coating. The low efficiency is mainly due to the low open-circuit voltage (Voc), which is attributed to high dark current caused by interface recombination at the ZnTe/CdTe interface. Low-temperature measurements show a linear increase in Voc with decreasing temperature down to 77 K, which suggests that the room-temperature operation is limited by non-radiative recombination. An open-circuit voltage of 1.22 V and an efficiency of 8.46 % is demonstrated at 77 K. It is expected that a coherently strained MgCdTe/CdTe/MgCdTe DH solar cell design will produce higher efficiency and Voc compared to the ZnTe/CdTe/MgCdTe design with relaxed ZnTe layer.
Undoped CdTe/MgCdTe DHs are first grown in order to determine the material quality of the CdTe epilayer and to optimize the growth conditions. DH samples show strong photoluminescence with over double the intensity as that of a GaAs/AlGaAs DH with an identical layer structure. Time-resolved photoluminescence of the CdTe/MgCdTe DH gives a carrier lifetime of up to 179 ns for a 2 µm thick CdTe layer, which is more than one order of magnitude longer than that of polycrystalline CdTe films. MgCdTe barrier layers are found to be effective at confining photogenerated carriers and have a relatively low interface recombination velocity of 461 cm/s. The optimal growth temperature and Cd/Te flux ratio is determined to be 265 °C and 1.5, respectively.
Monocrystalline ZnTe/CdTe/MgCdTe P-n-N DH solar cells are designed, grown, processed into solar cell devices, and characterized. A maximum efficiency of 6.11 % is demonstrated for samples without an anti-reflection coating. The low efficiency is mainly due to the low open-circuit voltage (Voc), which is attributed to high dark current caused by interface recombination at the ZnTe/CdTe interface. Low-temperature measurements show a linear increase in Voc with decreasing temperature down to 77 K, which suggests that the room-temperature operation is limited by non-radiative recombination. An open-circuit voltage of 1.22 V and an efficiency of 8.46 % is demonstrated at 77 K. It is expected that a coherently strained MgCdTe/CdTe/MgCdTe DH solar cell design will produce higher efficiency and Voc compared to the ZnTe/CdTe/MgCdTe design with relaxed ZnTe layer.
ContributorsDiNezza, Michael John (Author) / Zhang, Yong-Hang (Thesis advisor) / Johnson, Shane (Committee member) / Tao, Meng (Committee member) / Holman, Zachary (Committee member) / Arizona State University (Publisher)
Created2014
Description
In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET.
ContributorsAshraf, Nabil Shovon (Author) / Vasileska, Dragica (Thesis advisor) / Schroder, Dieter (Committee member) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
In semiconductor physics, many properties or phenomena of materials can be brought to light through certain changes in the materials. Having a tool to define new material properties so as to highlight certain phenomena greatly increases the ability to understand that phenomena. The generalized Monte Carlo tool allows the user to do that by keeping every parameter used to define a material, within the non-parabolic band approximation, a variable in the control of the user. A material is defined by defining its valleys, energies, valley effective masses and their directions. The types of scattering to be included can also be chosen. The non-parabolic band structure model is used. With the deployment of the generalized Monte Carlo tool onto www.nanoHUB.org the tool will be available to users around the world. This makes it a very useful educational tool that can be incorporated into curriculums. The tool is integrated with Rappture, to allow user-friendly access of the tool. The user can freely define a material in an easy systematic way without having to worry about the coding involved. The output results are automatically graphed and since the code incorporates an analytic band structure model, it is relatively fast. The versatility of the tool has been investigated and has produced results closely matching the experimental values for some common materials. The tool has been uploaded onto www.nanoHUB.org by integrating it with the Rappture interface. By using Rappture as the user interface, one can easily make changes to the current parameter sets to obtain even more accurate results.
ContributorsHathwar, Raghuraj (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Saraniti, Marco (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect.
ContributorsTierney, Brian David (Author) / Goodnick, Stephen (Thesis advisor) / Ferry, David (Committee member) / Akis, Richard (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
A dual chamber molecular beam epitaxy (MBE) system was rebuilt for the growth of 6.1 Angstrom II-VI and III-V compound semiconductor materials that are to be used in novel optoelectronic devices that take advantage of the nearly continuous bandgap availability between 0 eV and 3.4 eV. These devices include multijunction solar cells and multicolor detectors. The MBE system upgrade involved the conversion of a former III-V chamber for II-VI growth. This required intensive cleaning of the chamber and components to prevent contamination. Special features including valved II-VI sources and the addition of a cold trap allowed for the full system to be baked to 200 degrees Celsius to improve vacuum conditions and reduce background impurity concentrations in epilayers. After the conversion, the system was carefully calibrated and optimized for the growth of ZnSe and ZnTe on GaAs (001) substrates. Material quality was assessed using X-ray diffraction rocking curves. ZnSe layers displayed a trend of improving quality with decreasing growth temperature reaching a minimum full-width half-maximum (FWHM) of 113 arcsec at 278 degrees Celsius. ZnTe epilayer quality increased with growth temperature under Zn rich conditions attaining a FWHM of 84 arcsec at 440 degrees Celsius. RHEED oscillations were successfully observed and used to obtain growth rate in situ for varying flux and temperature levels. For a fixed flux ratio, growth rate decreased with growth temperature as the desorption rate increased. A directly proportional dependence of growth rate on Te flux was observed for Zn rich growth. Furthermore, a method for determining the flux ratio necessary for attaining the stoichiometric condition was demonstrated.
ContributorsDettlaff, W. Hank G (Author) / Zhang, Yong-Hang (Thesis advisor) / Vasileska, Dragica (Committee member) / Johnson, Shane (Committee member) / Arizona State University (Publisher)
Created2012
Description
This dissertation addresses challenges pertaining to multi-junction (MJ) solar cells from material development to device design and characterization. Firstly, among the various methods to improve the energy conversion efficiency of MJ solar cells using, a novel approach proposed recently is to use II-VI (MgZnCd)(SeTe) and III-V (AlGaIn)(AsSb) semiconductors lattice-matched on GaSb or InAs substrates for current-matched subcells with minimal defect densities. CdSe/CdTe superlattices are proposed as a potential candidate for a subcell in the MJ solar cell designs using this material system, and therefore the material properties of the superlattices are studied. The high structural qualities of the superlattices are obtained from high resolution X-ray diffraction measurements and cross-sectional transmission electron microscopy images. The effective bandgap energies of the superlattices obtained from the photoluminescence (PL) measurements vary with the layer thicknesses, and are smaller than the bandgap energies of either the constituent material. Furthermore, The PL peak position measured at the steady state exhibits a blue shift that increases with the excess carrier concentration. These results confirm a strong type-II band edge alignment between CdSe and CdTe. The valence band offset between unstrained CdSe and CdTe is determined as 0.63 eV±0.06 eV by fitting the measured PL peak positions using the Kronig-Penney model. The blue shift in PL peak position is found to be primarily caused by the band bending effect based on self-consistent solutions of the Schrödinger and Poisson equations. Secondly, the design of the contact grid layout is studied to maximize the power output and energy conversion efficiency for concentrator solar cells. Because the conventional minimum power loss method used for the contact design is not accurate in determining the series resistance loss, a method of using a distributed series resistance model to maximize the power output is proposed for the contact design. It is found that the junction recombination loss in addition to the series resistance loss and shadowing loss can significantly affect the contact layout. The optimal finger spacing and maximum efficiency calculated by the two methods are close, and the differences are dependent on the series resistance and saturation currents of solar cells. Lastly, the accurate measurements of external quantum efficiency (EQE) are important for the design and development of MJ solar cells. However, the electrical and optical couplings between the subcells have caused EQE measurement artifacts. In order to interpret the measurement artifacts, DC and small signal models are built for the bias condition and the scan of chopped monochromatic light in the EQE measurements. Characterization methods are developed for the device parameters used in the models. The EQE measurement artifacts are found to be caused by the shunt and luminescence coupling effects, and can be minimized using proper voltage and light biases. Novel measurement methods using a pulse voltage bias or a pulse light bias are invented to eliminate the EQE measurement artifacts. These measurement methods are nondestructive and easy to implement. The pulse voltage bias or pulse light bias is superimposed on the conventional DC voltage and light biases, in order to control the operating points of the subcells and counterbalance the effects of shunt and luminescence coupling. The methods are demonstrated for the first time to effectively eliminate the measurement artifacts.
ContributorsLi, Jingjing (Author) / Zhang, Yong-Hang (Thesis advisor) / Tao, Meng (Committee member) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis mainly focuses on the study of quantum efficiency (QE) and its measurement, especially for nanowires (NWs). First, a brief introduction of nano-technology and nanowire is given to describe my initial research interest. Next various fundamental kinds of recombination mechanisms are described; both for radiative and non-radiative processes. This is an introduction for defining the internal quantum efficiency (IQE). A relative IQE measurement method is shown following that. Then it comes to the major part of the thesis discussing a procedure of quantum efficiency measurement using photoluminescence (PL) method and an integrating sphere, which has not been much applied to nanowires (NWs). In fact this is a convenient and useful approach for evaluating the quality of NWs since it considers not only the PL emission but also the absorption of NWs. The process is well illustrated and performed with both wavelength-dependent and power-dependent measurements. The measured PLQE is in the range of 0.3% ~ 5.4%. During the measurement, a phenomenon called photodegradation is observed and examined by a set of power-dependence measurements. This effect can be a factor for underestimating the PLQE and a procedure is introduced during the sample preparation process which managed to reduce this effect for some degree.
ContributorsChen, Dongzi (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
Thermal effects in nano-scaled devices were reviewed and modeling methodologies to deal with this issue were discussed. The phonon energy balance equations model, being one of the important previous works regarding the modeling of heating effects in nano-scale devices, was derived. Then, detailed description was given on the Monte Carlo (MC) solution of the phonon Boltzmann Transport Equation. The phonon MC solver was developed next as part of this thesis. Simulation results of the thermal conductivity in bulk Si show good agreement with theoretical/experimental values from literature.
ContributorsYoo, Seung Kyung (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2015