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Advances in software and applications continue to demand advances in memory. The ideal memory would be non-volatile and have maximal capacity, speed, retention time, endurance, and radiation hardness while also having minimal physical size, energy usage, and cost. The programmable metallization cell (PMC) is an emerging memory technology that is

Advances in software and applications continue to demand advances in memory. The ideal memory would be non-volatile and have maximal capacity, speed, retention time, endurance, and radiation hardness while also having minimal physical size, energy usage, and cost. The programmable metallization cell (PMC) is an emerging memory technology that is likely to surpass flash memory in all the listed ideal memory characteristics. A comprehensive physics-based model is needed to fully understand PMC operation and aid in design optimization. With the intent of advancing the PMC modeling effort, this thesis presents two simulation models for the PMC. The first model is a finite element model based on Silvaco Atlas finite element analysis software. Limitations of the software are identified that make this model inconsistent with the operating mechanism of the PMC. The second model is a physics-based numerical model developed for the PMC. This model is successful in matching data measured from a chalcogenide glass PMC designed and manufactured at ASU. Matched operating characteristics observable in the current and resistance vs. voltage data include the OFF/ON resistances and write/erase and electrodeposition voltage thresholds. Multilevel programming is also explained and demonstrated with the numerical model. The numerical model has already proven useful by revealing some information presented about the operation and characteristics of the PMC.
ContributorsOleksy, David Ryan (Author) / Barnaby, Hugh J (Thesis advisor) / Kozicki, Michael N (Committee member) / Edwards, Arthur H (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Low Power, High Speed Analog to Digital Converters continues to remain one of the major building blocks for modern communication systems. Due to continuing trend of the aggressive scaling of the MOS devices, the susceptibility of most of the deep-sub micron CMOS technologies to the ionizing radiation has decreased over

Low Power, High Speed Analog to Digital Converters continues to remain one of the major building blocks for modern communication systems. Due to continuing trend of the aggressive scaling of the MOS devices, the susceptibility of most of the deep-sub micron CMOS technologies to the ionizing radiation has decreased over the period of time. When electronic circuits fabricated in these CMOS technologies are exposed to ionizing radiations, considerable change in the performance of circuits can be seen over a period of time. The change in the performance can be quantified in terms of decreasing linearity of the circuit which directly relates to the resolution of the circuit. Analog to Digital Converter is one of the most critical blocks of any electronic circuitry sent to space. The degradation in the performance of an Analog to Digital Converter due to radiation effects can jeopardize many research programs related to space. These radiation effects can completely hamper the working of a circuit. This thesis discusses the effects of Ionizing radiation on an 11 bit 325 MSPS pipeline ADC. The ADC is exposed to different doses of radiation and performance is compared.
ContributorsVashisth, Siddharth (Author) / Barnaby, Hugh J (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity

Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity of the material when a metal such as Ag or Cu is added to it by diffusion. This study demonstrates the potential radiation-sensing capabilities of two metal/chalcogenide glass device configurations. Lateral and vertical device configurations sense the radiation-induced migration of Ag+ ions in germanium selenide glasses via changes in electrical resistance between electrodes on the ChG. Before irradiation, these devices exhibit a high-resistance `OFF-state' (in the order of 10E12) but following irradiation, with either 60-Co gamma-rays or UV light, their resistance drops to a low-resistance `ON-state' (around 10E3). Lateral devices have exhibited cyclical recovery with room temperature annealing of the Ag doped ChG, which suggests potential uses in reusable radiation sensor applications. The feasibility of producing inexpensive flexible radiation sensors has been demonstrated by studying the effects of mechanical strain and temperature stress on sensors formed on flexible polymer substrate. The mechanisms of radiation-induced Ag/Ag+ transport and reactions in ChG have been modeled using a finite element device simulator, ATLAS. The essential reactions captured by the simulator are radiation-induced carrier generation, combined with reduction/oxidation for Ag species in the chalcogenide film. Metal-doped ChGs are solid electrolytes that have both ionic and electronic conductivity. The ChG based Programmable Metallization Cell (PMC) is a technology platform that offers electric field dependent resistance switching mechanisms by formation and dissolution of nano sized conductive filaments in a ChG solid electrolyte between oxidizable and inert electrodes. This study identifies silver anode agglomeration in PMC devices following large radiation dose exposure and considers device failure mechanisms via electrical and material characterization. The results demonstrate that by changing device structural parameters, silver agglomeration in PMC devices can be suppressed and reliable resistance switching may be maintained for extremely high doses ranging from 4 Mrad(GeSe) to more than 10 Mrad (ChG).
ContributorsDandamudi, Pradeep (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Committee member) / Holbert, Keith E. (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Microprocessors are the processing heart of any digital system and are central to all the technological advancements of the age including space exploration and monitoring. The demands of space exploration require a special class of microprocessors called radiation hardened microprocessors which are less susceptible to radiation present outside the earth's

Microprocessors are the processing heart of any digital system and are central to all the technological advancements of the age including space exploration and monitoring. The demands of space exploration require a special class of microprocessors called radiation hardened microprocessors which are less susceptible to radiation present outside the earth's atmosphere, in other words their functioning is not disrupted even in presence of disruptive radiation. The presence of these particles forces the designers to come up with design techniques at circuit and chip levels to alleviate the errors which can be encountered in the functioning of microprocessors. Microprocessor evolution has been very rapid in terms of performance but the same cannot be said about its rad-hard counterpart. With the total data processing capability overall increasing rapidly, the clear lack of performance of the processors manifests as a bottleneck in any processing system. To design high performance rad-hard microprocessors designers have to overcome difficult design problems at various design stages i.e. Architecture, Synthesis, Floorplanning, Optimization, routing and analysis all the while maintaining circuit radiation hardness. The reference design `HERMES' is targeted at 90nm IBM G process and is expected to reach 500Mhz which is twice as fast any processor currently available. Chapter 1 talks about the mechanisms of radiation effects which cause upsets and degradation to the functioning of digital circuits. Chapter 2 gives a brief description of the components which are used in the design and are part of the consistent efforts at ASUVLSI lab culminating in this chip level implementation of the design. Chapter 3 explains the basic digital design ASIC flow and the changes made to it leading to a rad-hard specific ASIC flow used in implementing this chip. Chapter 4 talks about the triple mode redundant (TMR) specific flow which is used in the block implementation, delineating the challenges faced and the solutions proposed to make the flow work. Chapter 5 explains the challenges faced and solutions arrived at while using the top-level flow described in chapter 3. Chapter 6 puts together the results and analyzes the design in terms of basic integrated circuit design constraints.
ContributorsRamamurthy, Chandarasekaran (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh J (Committee member) / Mayhew, David (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies

Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies for many electronic parts. Exposure to ionizing radiation increases the density of oxide and interfacial defects in bipolar oxides leading to an increase in base current in bipolar junction transistors. Radiation-induced excess base current is the primary cause of current gain degradation. Analysis of base current response can enable the measurement of defects generated by radiation exposure. In addition to radiation, the space environment is also characterized by extreme temperature fluctuations. Temperature, like radiation, also has a very strong impact on base current. Thus, a technique for separating the effects of radiation from thermal effects is necessary in order to accurately measure radiation-induced damage in space. This thesis focuses on the extraction of radiation damage in lateral PNP bipolar junction transistors and the space environment. It also describes the measurement techniques used and provides a quantitative analysis methodology for separating radiation and thermal effects on the bipolar base current.
ContributorsCampola, Michael J (Author) / Barnaby, Hugh J (Thesis advisor) / Holbert, Keith E. (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated

The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
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Description
A modeling platform for predicting total ionizing dose (TID) and dose rate response of commercial commercial-off-the-shelf (COTS) linear bipolar circuits and technologies is introduced. Tasks associated with the modeling platform involve the development of model to predict the excess current response in a bipolar transistor given inputs of interface (NIT)

A modeling platform for predicting total ionizing dose (TID) and dose rate response of commercial commercial-off-the-shelf (COTS) linear bipolar circuits and technologies is introduced. Tasks associated with the modeling platform involve the development of model to predict the excess current response in a bipolar transistor given inputs of interface (NIT) and oxide defects (NOT) which are caused by ionizing radiation exposure. Existing models that attempt to predict this excess base current response are derived and discussed in detail. An improved model is proposed which modifies the existing model and incorporates the impact of charged interface trap defects on radiation-induced excess base current. The improved accuracy of the new model in predicting excess base current response in lateral PNP (LPNP) is then verified with Technology Computer Aided Design (TCAD) simulations. Finally, experimental data and compared with the improved and existing model calculations.
ContributorsTolleson, Blayne S. (Author) / Barnaby, Hugh J (Thesis advisor) / Gonzalez-Velo, Yago (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2017
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Description
High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing

High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use.

In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.
ContributorsFang, Runchen (Author) / Barnaby, Hugh J (Thesis advisor) / Kozicki, Michael N (Thesis advisor) / Vasileska, Dragica (Committee member) / Thornton, Trevor J (Committee member) / Arizona State University (Publisher)
Created2018
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Description
This work investigates the effects of ionizing radiation and displacement damage on the retention of state, DC programming, and neuromorphic pulsed programming of Ag-Ge30Se70 conductive bridging random access memory (CBRAM) devices. The results show that CBRAM devices are susceptible to both environments. An observable degradation in electrical response due to

This work investigates the effects of ionizing radiation and displacement damage on the retention of state, DC programming, and neuromorphic pulsed programming of Ag-Ge30Se70 conductive bridging random access memory (CBRAM) devices. The results show that CBRAM devices are susceptible to both environments. An observable degradation in electrical response due to total ionizing dose (TID) is shown during neuromorphic pulsed programming at TID below 1 Mrad using Cobalt-60. DC cycling in a 14 MeV neutron environment showed a collapse of the high resistance state (HRS) and low resistance state (LRS) programming window after a fluence of 4.9x10^{12} n/cm^2, demonstrating the CBRAM can fail in a displacement damage environment. Heavy ion exposure during retention testing and DC cycling, showed that failures to programming occurred at approximately the same threshold, indicating that the failure mechanism for the two types of tests may be the same. The dose received due to ionizing electronic interactions and non-ionizing kinetic interactions, was calculated for each ion species at the fluence of failure. TID values appear to be the most correlated, indicating that TID effects may be the dominate failure mechanism in a combined environment, though it is currently unclear as to how the displacement damage also contributes to the response. An analysis of material effects due to TID has indicated that radiation damage can limit the migration of Ag+ ions. The reduction in ion current density can explain several of the effects observed in CBRAM while in the LRS.
ContributorsTaggart, Jennifer L (Author) / Barnaby, Hugh J (Thesis advisor) / Kozicki, Michael N (Committee member) / Holbert, Keith E. (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2018
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Description
High speed image sensors are used as a diagnostic tool to analyze high speed processes for industrial, automotive, defense and biomedical application. The high fame rate of these sensors, capture a series of images that enables the viewer to understand and analyze the high speed phenomena. However, the pixel readout

High speed image sensors are used as a diagnostic tool to analyze high speed processes for industrial, automotive, defense and biomedical application. The high fame rate of these sensors, capture a series of images that enables the viewer to understand and analyze the high speed phenomena. However, the pixel readout circuits designed for these sensors with a high frame rate (100fps to 1 Mfps) have a very low fill factor which are less than 58%. For high speed operation, the exposure time is less and (or) the light intensity incident on the image sensor is less. This makes it difficult for the sensor to detect faint light signals and gives a lower limit on the signal levels being detected by the sensor. Moreover, the leakage paths in the pixel readout circuit also sets a limit on the signal level being detected. Therefore, the fill factor of the pixel should be maximized and the leakage currents in the readout circuits should be minimized.

This thesis work presents the design of the pixel readout circuit suitable for high speed and low light imaging application. The circuit is an improvement to the 6T pixel readout architecture. The designed readout circuit minimizes the leakage currents in the circuit and detects light producing a signal level of 350µV at the cathode of the photodiode. A novel layout technique is used for the pixel, which improves the fill factor of the pixel to 64.625%. The read out circuit designed is an integral part of high speed image sensor, which is fabricated using a 0.18 µm CMOS technology with the die size of 3.1mm x 3.4 mm, the pixel size of 20µm x 20 µm, number of pixel of 96 x 96 and four 10-bit pipelined ADC’s. The image sensor achieves a high frame rate of 10508 fps and readout speed of 96 M pixels / sec.
ContributorsZol, Akshay (Author) / Barnaby, Hugh J (Thesis advisor) / Mikkola, Esko O (Committee member) / Kitchen, Jennifer N (Committee member) / Arizona State University (Publisher)
Created2016