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Description
High-Resistivity Silicon (HRS) substrates are important for low-loss, high-performance microwave and millimeter wave devices in high-frequency telecommunication systems. The highest resistivity of up to ~10,000 ohm.cm is Float Zone (FZ) grown Si which is produced in small quantities and moderate wafer diameter. The more common Czochralski (CZ) Si can achieve

High-Resistivity Silicon (HRS) substrates are important for low-loss, high-performance microwave and millimeter wave devices in high-frequency telecommunication systems. The highest resistivity of up to ~10,000 ohm.cm is Float Zone (FZ) grown Si which is produced in small quantities and moderate wafer diameter. The more common Czochralski (CZ) Si can achieve resistivities of around 1000 ohm.cm, but the wafers contain oxygen that can lead to thermal donor formation with donor concentration significantly higher (~1015 cm-3) than the dopant concentration (~1012-1013 cm-3) of such high-resistivity Si leading to resistivity changes and possible type conversion of high-resistivity p-type silicon. In this research capacitance-voltage (C-V) characterization is employed to study the donor formation and type conversion of p-type High-resistivity Silicon-On-Insulator (HRSOI) wafers and the challenges involved in C-V characterization of HRSOI wafers using a Schottky contact are highlighted. The maximum capacitance of bulk or Silicon-On-Insulator (SOI) wafers is governed by the gate/contact area. During C-V characterization of high-resistivity SOI wafers with aluminum contacts directly on the Si film (Schottky contact); it was observed that the maximum capacitance is much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and the buried oxide capacitance. In addition, an "S"-shape C-V plot was observed in the accumulation region. The effects of various factors, such as: frequency, contact and substrate sizes, gate oxide, SOI film thickness, film and substrate doping, carrier lifetime, contact work-function, temperature, light, annealing temperature and radiation on the C-V characteristics of HRSOI wafers are studied. HRSOI wafers have the best crosstalk prevention capability compared to other types of wafers, which plays a major role in system-on-chip configuration to prevent coupling between high frequency digital and sensitive analog circuits. Substrate crosstalk in HRSOI and various factors affecting the crosstalk, such as: substrate resistivity, separation between devices, buried oxide (BOX) thickness, radiation, temperature, annealing, light, and device types are discussed. Also various ways to minimize substrate crosstalk are studied and a new characterization method is proposed. Owing to their very low doping concentrations and the presence of oxygen in CZ wafers, HRS wafers pose a challenge in resistivity measurement using conventional techniques such as four-point probe and Hall measurement methods. In this research the challenges in accurate resistivity measurement using four-point probe, Hall method, and C-V profile are highlighted and a novel approach to extract resistivity of HRS wafers based on Impedance Spectroscopy measurements using polymer dielectrics such as Polystyrene and Poly Methyl Methacrylate (PMMA) is proposed.
ContributorsNayak, Pinakpani (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
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Description
This thesis mainly focuses on the study of quantum efficiency (QE) and its measurement, especially for nanowires (NWs). First, a brief introduction of nano-technology and nanowire is given to describe my initial research interest. Next various fundamental kinds of recombination mechanisms are described; both for radiative and non-radiative processes. This

This thesis mainly focuses on the study of quantum efficiency (QE) and its measurement, especially for nanowires (NWs). First, a brief introduction of nano-technology and nanowire is given to describe my initial research interest. Next various fundamental kinds of recombination mechanisms are described; both for radiative and non-radiative processes. This is an introduction for defining the internal quantum efficiency (IQE). A relative IQE measurement method is shown following that. Then it comes to the major part of the thesis discussing a procedure of quantum efficiency measurement using photoluminescence (PL) method and an integrating sphere, which has not been much applied to nanowires (NWs). In fact this is a convenient and useful approach for evaluating the quality of NWs since it considers not only the PL emission but also the absorption of NWs. The process is well illustrated and performed with both wavelength-dependent and power-dependent measurements. The measured PLQE is in the range of 0.3% ~ 5.4%. During the measurement, a phenomenon called photodegradation is observed and examined by a set of power-dependence measurements. This effect can be a factor for underestimating the PLQE and a procedure is introduced during the sample preparation process which managed to reduce this effect for some degree.
ContributorsChen, Dongzi (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Thermal effects in nano-scaled devices were reviewed and modeling methodologies to deal with this issue were discussed. The phonon energy balance equations model, being one of the important previous works regarding the modeling of heating effects in nano-scale devices, was derived. Then, detailed description was given on the Monte Carlo

Thermal effects in nano-scaled devices were reviewed and modeling methodologies to deal with this issue were discussed. The phonon energy balance equations model, being one of the important previous works regarding the modeling of heating effects in nano-scale devices, was derived. Then, detailed description was given on the Monte Carlo (MC) solution of the phonon Boltzmann Transport Equation. The phonon MC solver was developed next as part of this thesis. Simulation results of the thermal conductivity in bulk Si show good agreement with theoretical/experimental values from literature.
ContributorsYoo, Seung Kyung (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2015
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Description
GaAs single-junction solar cells have been studied extensively in recent years, and have reached over 28 % efficiency. Further improvement requires an optically thick but physically thin absorber to provide both large short-circuit current and high open-circuit voltage. By detailed simulation, it is concluded that ultra-thin GaAs cells with hundreds

GaAs single-junction solar cells have been studied extensively in recent years, and have reached over 28 % efficiency. Further improvement requires an optically thick but physically thin absorber to provide both large short-circuit current and high open-circuit voltage. By detailed simulation, it is concluded that ultra-thin GaAs cells with hundreds of nanometers thickness and reflective back scattering can potentially offer efficiencies greater than 30 %. The 300 nm GaAs solar cell with AlInP/Au reflective back scattering is carefully designed and demonstrates an efficiency of 19.1 %. The device performance is analyzed using the semi-analytical model with Phong distribution implemented to account for non-Lambertian scattering. A Phong exponent m of ~12, a non-radiative lifetime of 130 ns, and a specific series resistivity of 1.2 Ω·cm2 are determined.

Thin-film CdTe solar cells have also attracted lots of attention due to the continuous improvements in their device performance. To address the issue of the lower efficiency record compared to detailed-balance limit, the single-crystalline Cd(Zn)Te/MgCdTe double heterostructures (DH) grown on InSb (100) substrates by molecular beam epitaxy (MBE) are carefully studied. The Cd0.9946Zn0.0054Te alloy lattice-matched to InSb has been demonstrated with a carrier lifetime of 0.34 µs observed in a 3 µm thick Cd0.9946Zn0.0054Te/MgCdTe DH sample. The substantial improvement of lifetime is due to the reduction in misfit dislocation density. The recombination lifetime and interface recombination velocity (IRV) of CdTe/MgxCd1-xTe DHs are investigated. The IRV is found to be dependent on both the MgCdTe barrier height and width due to the thermionic emission and tunneling processes. A record-long carrier lifetime of 2.7 µs and a record-low IRV of close to zero have been confirmed experimentally.

The MgCdTe/Si tandem solar cell is proposed to address the issue of high manufacturing costs and poor performance of thin-film solar cells. The MBE grown MgxCd1-xTe/MgyCd1-yTe DHs have demonstrated the required bandgap energy of 1.7 eV, a carrier lifetime of 11 ns, and an effective IRV of (1.869 ± 0.007) × 103 cm/s. The large IRV is attributed to thermionic-emission induced interface recombination. These understandings can be applied to fabricating the high-efficiency low-cost MgCdTe/Si tandem solar cell.
ContributorsLiu, Shi (Author) / Zhang, Yong-Hang (Thesis advisor) / Johnson, Shane R (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
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Description
Thin-film modules of all technologies often suffer from performance degradation over time. Some of the performance changes are reversible and some are not, which makes deployment, testing, and energy-yield prediction more challenging. The most commonly alleged causes of instability in CdTe device, such as “migration of Cu,” have been investigated

Thin-film modules of all technologies often suffer from performance degradation over time. Some of the performance changes are reversible and some are not, which makes deployment, testing, and energy-yield prediction more challenging. The most commonly alleged causes of instability in CdTe device, such as “migration of Cu,” have been investigated rigorously over the past fifteen years. As all defects, intrinsic or extrinsic, interact with the electrical potential and free carriers so that charged defects may drift in the electric field and changing ionization state with excess free carriers. Such complexity of interactions in CdTe makes understanding of temporal changes in device performance even more challenging. The goal of the work in this dissertation is, thus, to eliminate the ambiguity between the observed performance changes under stress and their physical root cause by enabling a depth of modeling that takes account of diffusion and drift at the atomistic level coupled to the electronic subsystem responsible for a PV device’s function. The 1D Unified Solver, developed as part of this effort, enables us to analyze PV devices at a greater depth.

In this dissertation, the implementation of a drift-diffusion model defect migration simulator, development of an implicit reaction scheme for total mass conservation, and a couple of other numerical schemes to improve the overall flexibility and robustness of this coupled Unified Solver is discussed. Preliminary results on Cu (with or without Cl-treatment) annealing simulations in both single-crystal CdTe wafer and poly-crystalline CdTe devices show promising agreement to experimental findings, providing a new perspective in the research of improving doping concentration hence the open-circuit voltage of CdTe technology. Furthermore, on the reliability side, in agreement of previous experimental reports, simulation results suggest possibility of Cu depletion in short-circuited cells stressed at elevated temperature. The developed solver also successfully demonstrated that mobile donor migration can be used to explain solar cell performance changes under different stress conditions.
ContributorsGuo, Da (Author) / Vasileska, Dragica (Thesis advisor) / Sankin, Igor (Committee member) / Goodnick, Stephen (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2017
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Description
Semiconductor nanowires have the potential to emerge as the building blocks of next generation field-effect transistors, logic gates, solar cells and light emitting diodes. Use of Gallium Nitride (GaN) and other wide bandgap materials combines the advantages of III-nitrides along with the enhanced mobility offered by 2-dimensional confinement present in

Semiconductor nanowires have the potential to emerge as the building blocks of next generation field-effect transistors, logic gates, solar cells and light emitting diodes. Use of Gallium Nitride (GaN) and other wide bandgap materials combines the advantages of III-nitrides along with the enhanced mobility offered by 2-dimensional confinement present in nanowires. The focus of this thesis is on developing a low field mobility model for a GaN nanowire using Ensemble Monte Carlo (EMC) techniques. A 2D Schrödinger-Poisson solver and a one-dimensional Monte Carlo solver is developed for an Aluminum Gallium Nitride/Gallium Nitride Heterostructure nanowire. A GaN/AlN/AlGaN heterostructure device is designed which creates 2-dimensional potential well for electrons. The nanowire is treated as a quasi-1D system in this work. A self-consistent 2D Schrödinger-Poisson solver is designed which determines the subband energies and the corresponding wavefunctions of the confined system. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering and piezoelectric scattering are considered to account for the electron phonon interactions in the system. Overlap integrals and 1D scattering rate expressions are derived for all the mechanisms listed. A generic one-dimensional Monte Carlo solver is also developed. Steady state results from the 1D Monte Carlo solver are extracted to determine the low field mobility of the GaN nanowires.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2017
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Description
In this thesis, the methods of aluminum electroplating in an ionic liquid for silicon solar cell front side metallization were studied. It focused on replacing the current silver screen printing with an alternative metallization technology using a low-cost Earth-abundant metal for mass production, due to the high cost and limited

In this thesis, the methods of aluminum electroplating in an ionic liquid for silicon solar cell front side metallization were studied. It focused on replacing the current silver screen printing with an alternative metallization technology using a low-cost Earth-abundant metal for mass production, due to the high cost and limited availability of silver. A conventional aluminum electroplating method was employed for silicon solar cells fabrication on both p-type and n-type substrates. The highest efficiency of 17.9% was achieved in the n-type solar cell with a rear junction, which is comparable to that of the same structure cell with screen printed silver electrodes from industrial production lines. It also showed better spiking resistant performance than the common structure p-type solar cell. Further efforts were put on the development of a novel light-induced plating of aluminum technique. The aluminum was deposited directly on a silicon substrate without the assistance of a conductive seed layer, thus simplified and reduced the process cost. The plated aluminum has good adhesion to the silicon surface with the resistivity as low as 4×10–6 -cm. A new demo tool was designed and set up for the light-induced plating experiment, aiming to utilize this technique in large-size solar cells fabrication and mass production. Besides the metallization methods, a comprehensive sensitivity analysis for the efficiency dispersion in the production of crystalline-Si solar cells was presented based on numerical simulations. Temperature variation in the diffusion furnace was the most significant cause of the efficiency dispersion. It was concluded that a narrow efficiency range of ±0.5% absolute is achievable if the emitter diffusion temperature is confined to a 13˚C window, while other cell parameters vary within their normal windows. Possible methods to minimize temperature variation in emitter diffusion were proposed.
ContributorsWang, Laidong (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2018
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Description
High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing

High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use.

In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.
ContributorsFang, Runchen (Author) / Barnaby, Hugh J (Thesis advisor) / Kozicki, Michael N (Thesis advisor) / Vasileska, Dragica (Committee member) / Thornton, Trevor J (Committee member) / Arizona State University (Publisher)
Created2018
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Description
Silicon photovoltaics (PV) is approaching its theoretical efficiency limit as a single-junction technology. To break this limit and further lower the PV-generated levelized cost of electricity, it is necessary to engineer a silicon-based “tandem” technology in which a solar cell of another material is stacked on top of silicon to

Silicon photovoltaics (PV) is approaching its theoretical efficiency limit as a single-junction technology. To break this limit and further lower the PV-generated levelized cost of electricity, it is necessary to engineer a silicon-based “tandem” technology in which a solar cell of another material is stacked on top of silicon to make more efficient use of the full solar spectrum.

This dissertation understands and develops four aspects of silicon-based tandem PV technology. First, a new “spectral efficiency” concept is proposed to understand how tandem cells should be designed and to identify the best tandem partners for silicon cells. Using spectral efficiency, a top-cell-design guide is constructed for silicon-based tandems that sets efficiency targets for top cells with various bandgaps to achieve targeted tandem efficiencies.

Second, silicon heterojunction solar cells are tuned to the near-infrared spectrum to enable world-record perovskite/silicon tandems both in two- and four-terminal configurations. In particular, for the 23.6%-efficient two-terminal tandem, a single-side textured silicon bottom cell is fabricated with a low-refractive-index silicon nanoparticle layer as a rear reflector. This design boosts the current density to 18.5 mA/cm2; this value exceeds that of any other silicon bottom cell and matches that of the top cell.

Third, “PVMirrors” are proposed as a novel tandem architecture to integrate silicon cells with various top cells. A strength of the design is that the PVMirror collects diffuse light as a concentrating technology. With this concept, a gallium-arsenide/silicon PVMirror tandem is demonstrated with an outdoor efficiency of 29.6%, with respect to the global irradiance.

Finally, a simple and versatile analytical model is constructed to evaluate the cost competitiveness of an arbitrary tandem against its sub-cell alternatives. It indicates that tandems will become increasingly attractive in the market, as the ratio of sub-cell module cost to area-related balance-of-system cost—the key metric that will determine the market success or failure of tandems—is decreasing.

As an evolution of silicon technology, silicon-based tandems are the future of PV. They will allow more people to have access to clean energy at ultra-low cost. This thesis defines both the technological and economic landscape of silicon-based tandems, and makes important contributions to this tandem future.
ContributorsYu, Zhengshan (Author) / Holman, Zachary C (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Bowden, Stuart G (Committee member) / King, Richard R (Committee member) / Arizona State University (Publisher)
Created2018
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Description
This dissertation details a study of wide-bandgap molecular beam epitaxy (MBE)-grown single-crystal MgxCd1-xTe. The motivation for this study is to open a pathway to reduced $/W solar power generation through the development of a high-efficiency 1.7-eV II-VI top cell current-matched to low-cost 1.1-eV silicon. This paper reports the demonstration of

This dissertation details a study of wide-bandgap molecular beam epitaxy (MBE)-grown single-crystal MgxCd1-xTe. The motivation for this study is to open a pathway to reduced $/W solar power generation through the development of a high-efficiency 1.7-eV II-VI top cell current-matched to low-cost 1.1-eV silicon. This paper reports the demonstration of monocrystalline 1.7-eV MgxCd1-xTe/MgyCd1-yTe (y>x) double heterostructures (DHs) with a record carrier lifetime of 560 nanoseconds, along with a 1.7-eV MgxCd1-xTe/MgyCd1-yTe (y>x) single-junction solar cell with a record active-area efficiency of 15.2% and a record open-circuit voltage (VOC) of 1.176 V. A study of indium-doped n-type 1.7-eV MgxCd1-xTe with a carrier activation of up to 5 × 1017 cm-3 is presented with promise to increase device VOC. Finally, this paper reports an epitaxial lift-off (ELO) technology using water-soluble MgTe for the creation of free-standing MBE-grown II-VI single-crystal CdTe and 1.7-eV MgxCd1-xTe solar cells freed from lattice-matched InSb(001) substrates. Photoluminescence (PL) spectroscopy measurements comparing intact and free-standing films reveal the survival of optical quality in CdTe DHs after ELO. This technology opens up several possibilities to drastically increase cell conversion efficiency through improved light management and transferability into monolithic multijunction devices. Lastly, this report will present considerations for future work in each of the study areas mentioned above.
ContributorsCampbell, Calli Michele (Author) / Zhang, Yong-Hang (Thesis advisor) / Chan, Candance K (Committee member) / King, Richard R (Committee member) / Arizona State University (Publisher)
Created2019