Matching Items (56)
Filtering by
- All Subjects: Electrical Engineering
- Genre: Doctoral Dissertation
- Creators: Vasileska, Dragica
Description
This work is focused on modeling the reliability concerns in GaN HEMT technology. The two main reliability concerns in GaN HEMTs are electromechanical coupling and current collapse. A theoretical model was developed to model the piezoelectric polarization charge dependence on the applied gate voltage. As the sheet electron density in the channel increases, the influence of electromechanical coupling reduces as the electric field in the comprising layers reduces. A Monte Carlo device simulator that implements the theoretical model was developed to model the transport in GaN HEMTs. It is observed that with the coupled formulation, the drain current degradation in the device varies from 2%-18% depending on the gate voltage. Degradation reduces with the increase in the gate voltage due to the increase in the electron gas density in the channel. The output and transfer characteristics match very well with the experimental data. An electro-thermal device simulator was developed coupling the Monte Caro-Poisson solver with the energy balance solver for acoustic and optical phonons. An output current degradation of around 2-3 % at a drain voltage of 5V due to self-heating was observed. It was also observed that the electrostatics near the gate to drain region of the device changes due to the hot spot created in the device from self heating. This produces an electric field in the direction of accelerating the electrons from the channel to surface states. This will aid to the current collapse phenomenon in the device. Thus, the electric field in the gate to drain region is very critical for reliable performance of the device. Simulations emulating the charging of the surface states were also performed and matched well with experimental data. Methods to improve the reliability performance of the device were also investigated in this work. A shield electrode biased at source potential was used to reduce the electric field in the gate to drain extension region. The hot spot position was moved away from the critical gate to drain region towards the drain as the shield electrode length and dielectric thickness were being altered.
ContributorsPadmanabhan, Balaji (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Alford, Terry L. (Committee member) / Venkatraman, Prasad (Committee member) / Arizona State University (Publisher)
Created2013
Description
New technologies enable the exploration of space, high-fidelity defense systems, lighting fast intercontinental communication systems as well as medical technologies that extend and improve patient lives. The basis for these technologies is high reliability electronics devised to meet stringent design goals and to operate consistently for many years deployed in the field. An on-going concern for engineers is the consequences of ionizing radiation exposure, specifically total dose effects. For many of the different applications, there is a likelihood of exposure to radiation, which can result in device degradation and potentially failure. While the total dose effects and the resulting degradation are a well-studied field and methodologies to help mitigate degradation have been developed, there is still a need for simulation techniques to help designers understand total dose effects within their design. To that end, the work presented here details simulation techniques to analyze as well as predict the total dose response of a circuit. In this dissertation the total dose effects are broken into two sub-categories, intra-device and inter-device effects in CMOS technology. Intra-device effects degrade the performance of both n-channel and p-channel transistors, while inter-device effects result in loss of device isolation. In this work, multiple case studies are presented for which total dose degradation is of concern. Through the simulation techniques, the individual device and circuit responses are modeled post-irradiation. The use of these simulation techniques by circuit designers allow predictive simulation of total dose effects, allowing focused design changes to be implemented to increase radiation tolerance of high reliability electronics.
ContributorsSchlenvogt, Garrett (Author) / Barnaby, Hugh (Thesis advisor) / Goodnick, Stephen (Committee member) / Vasileska, Dragica (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Silicon solar cells with heterojunction carrier collectors based on a-Si/c-Si heterojunction (SHJ) have a potential to overcome the limitations of the conventional diffused junction solar cells and become the next industry standard manufacturing technology of solar cells. A brand feature of SHJ technology is ultrapassivated surfaces with already demonstrated 750 mV open circuit voltages (Voc) and 24.7% efficiency on large area solar cell. Despite very good results achieved in research and development, large volume manufacturing of high efficiency SHJ cells remains a fundamental challenge. The main objectives of this work were to develop a SHJ solar cell fabrication flow using industry compatible tools and processes in a pilot production environment, study the interactions between the used fabrication steps, identify the minimum set of optimization parameters and characterization techniques needed to achieve 20% baseline efficiency, and analyze the losses of power in fabricated SHJ cells by numerical and analytical modeling. This manuscript presents a detailed description of a SHJ solar cell fabrication flow developed at ASU Solar Power Laboratory (SPL) which allows large area solar cells with >750 mV Voc. SHJ cells on 135 um thick 153 cm2 area wafers with 19.5% efficiency were fabricated. Passivation quality of (i)a-Si:H film, bulk conductivity of doped a-Si films, bulk conductivity of ITO, transmission of ITO and the thickness of all films were identified as the minimum set of optimization parameters necessary to set up a baseline high efficiency SHJ fabrication flow. The preparation of randomly textured wafers to minimize the concentration of surface impurities and to avoid epitaxial growth of a-Si films was found to be a key challenge in achieving a repeatable and uniform passivation. This work resolved this issue by using a multi-step cleaning process based on sequential oxidation in nitric/acetic acids, Piranha and RCA-b solutions. The developed process allowed state of the art surface passivation with perfect repeatability and negligible reflectance losses. Two additional studies demonstrated 750 mV local Voc on 50 micron thick SHJ solar cell and < 1 cm/s effective surface recombination velocity on n-type wafers passivated by a-Si/SiO2/SiNx stack.
ContributorsHerasimenka, Stanislau Yur'yevich (Author) / Honsberg, C. (Christiana B.) (Thesis advisor) / Bowden, Stuart G (Thesis advisor) / Tracy, Clarence (Committee member) / Vasileska, Dragica (Committee member) / Holman, Zachary (Committee member) / Sinton, Ron (Committee member) / Arizona State University (Publisher)
Created2013
Description
Zinc oxide (ZnO), a naturally n-type semiconductor has been identified as a promising candidate to replace indium tin oxide (ITO) as the transparent electrode in solar cells, because of its wide bandgap (3.37 eV), abundant source materials and suitable refractive index (2.0 at 600 nm). Spray deposition is a convenient and low cost technique for large area and uniform deposition of semiconductor thin films. In particular, it provides an easier way to dope the film by simply adding the dopant precursor into the starting solution. In order to reduce the resistivity of undoped ZnO, many works have been done by doping in the ZnO with either group IIIA elements or VIIA elements using spray pyrolysis. However, the resistivity is still too high to meet TCO's resistivity requirement. In the present work, a novel co-spray deposition technique is developed to bypass a fundamental limitation in the conventional spray deposition technique, i.e. the deposition of metal oxides from incompatible precursors in the starting solution. With this technique, ZnO films codoped with one cationic dopant, Al, Cr, or Fe, and an anionic dopant, F, have been successfully synthesized, in which F is incompatible with all these three cationic dopants. Two starting solutions were prepared and co-sprayed through two separate spray heads. One solution contained only the F precursor, NH 4F. The second solution contained the Zn and one cationic dopant precursors, Zn(O 2CCH 3) 2 and AlCl 3, CrCl 3, or FeCl 3. The deposition was carried out at 500 °C; on soda-lime glass in air. Compared to singly-doped ZnO thin films, codoped ZnO samples showed better electrical properties. Besides, a minimum sheet resistance, 55.4 Ω/sq, was obtained for Al and F codoped ZnO films after vacuum annealing at 400 °C;, which was lower than singly-doped ZnO with either Al or F. The transmittance for the Al and F codoped ZnO samples was above 90% in the visible range. This co-spray deposition technique provides a simple and cost-effective way to synthesize metal oxides from incompatible precursors with improved properties.
ContributorsZhou, Bin (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
Nanolasers represents the research frontier in both the areas of photonics and nanotechnology for its interesting properties in low dimension physics, its appealing prospects in integrated photonics, and other on-chip applications. In this thesis, I present my research work on fabrication and characterization of a new type of nanolasers: metallic cavity nanolasers. The last ten years witnessed a dramatic paradigm shift from pure dielectric cavity to metallic cavity in the research of nanolasers. By using low loss metals such as silver, which is highly reflective at near infrared, light can be confined in an ultra small cavity or waveguide with sub-wavelength dimensions, thus enabling sub-wavelength cavity lasers. Based on this idea, I fabricated two different kinds of metallic cavity nanolasers with rectangular and circular geometries with InGaAs as the gain material and silver as the metallic shell. The lasing wavelength is around 1.55 μm, intended for optical communication applications. Continuous wave (CW) lasing at cryogenic temperature under current injection was achieved on devices with a deep sub-wavelength physical cavity volume smaller than 0.2 λ3. Improving device fabrication process is one of the main challenges in the development of metallic cavity nanolasers due to its ultra-small size. With improved fabrication process and device design, CW lasing at room temperature was demonstrated as well on a sub-wavelength rectangular device with a physical cavity volume of 0.67 λ3. Experiments verified that a small circular nanolasers supporting TE¬01 mode can generate an azimuthal polarized laser beam, providing a compact such source under electrical injection. Sources with such polarizations could have many special applications. Study of digital modulation of circular nanolasers showed that laser noise is an important factor that will affect the data rate of the nanolaser when used as the light source in optical interconnects. For future development, improving device fabrication processes is required to improve device performance. In addition, techniques need to be developed to realize nanolaser/Si waveguide integration. In essence, resolving these two critical issues will finally pave the way for these nanolasers to be used in various practical applications.
ContributorsDing, Kang (Author) / Ning, Cun-Zheng (Thesis advisor) / Yu, Hongbin (Committee member) / Palais, Joseph (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
Description
There has been recent interest in demonstrating solar cells which approach the detailed-balance or thermodynamic efficiency limit in order to establish a model system for which mass-produced solar cells can be designed. Polycrystalline CdS/CdTe heterostructures are currently one of many competing solar cell material systems. Despite being polycrystalline, efficiencies up to 21 % have been demonstrated by the company First Solar. However, this efficiency is still far from the detailed-balance limit of 32.1 % for CdTe. This work explores the use of monocrystalline CdTe/MgCdTe and ZnTe/CdTe/MgCdTe double heterostructures (DHs) grown on (001) InSb substrates by molecular beam epitaxy (MBE) for photovoltaic applications.
Undoped CdTe/MgCdTe DHs are first grown in order to determine the material quality of the CdTe epilayer and to optimize the growth conditions. DH samples show strong photoluminescence with over double the intensity as that of a GaAs/AlGaAs DH with an identical layer structure. Time-resolved photoluminescence of the CdTe/MgCdTe DH gives a carrier lifetime of up to 179 ns for a 2 µm thick CdTe layer, which is more than one order of magnitude longer than that of polycrystalline CdTe films. MgCdTe barrier layers are found to be effective at confining photogenerated carriers and have a relatively low interface recombination velocity of 461 cm/s. The optimal growth temperature and Cd/Te flux ratio is determined to be 265 °C and 1.5, respectively.
Monocrystalline ZnTe/CdTe/MgCdTe P-n-N DH solar cells are designed, grown, processed into solar cell devices, and characterized. A maximum efficiency of 6.11 % is demonstrated for samples without an anti-reflection coating. The low efficiency is mainly due to the low open-circuit voltage (Voc), which is attributed to high dark current caused by interface recombination at the ZnTe/CdTe interface. Low-temperature measurements show a linear increase in Voc with decreasing temperature down to 77 K, which suggests that the room-temperature operation is limited by non-radiative recombination. An open-circuit voltage of 1.22 V and an efficiency of 8.46 % is demonstrated at 77 K. It is expected that a coherently strained MgCdTe/CdTe/MgCdTe DH solar cell design will produce higher efficiency and Voc compared to the ZnTe/CdTe/MgCdTe design with relaxed ZnTe layer.
Undoped CdTe/MgCdTe DHs are first grown in order to determine the material quality of the CdTe epilayer and to optimize the growth conditions. DH samples show strong photoluminescence with over double the intensity as that of a GaAs/AlGaAs DH with an identical layer structure. Time-resolved photoluminescence of the CdTe/MgCdTe DH gives a carrier lifetime of up to 179 ns for a 2 µm thick CdTe layer, which is more than one order of magnitude longer than that of polycrystalline CdTe films. MgCdTe barrier layers are found to be effective at confining photogenerated carriers and have a relatively low interface recombination velocity of 461 cm/s. The optimal growth temperature and Cd/Te flux ratio is determined to be 265 °C and 1.5, respectively.
Monocrystalline ZnTe/CdTe/MgCdTe P-n-N DH solar cells are designed, grown, processed into solar cell devices, and characterized. A maximum efficiency of 6.11 % is demonstrated for samples without an anti-reflection coating. The low efficiency is mainly due to the low open-circuit voltage (Voc), which is attributed to high dark current caused by interface recombination at the ZnTe/CdTe interface. Low-temperature measurements show a linear increase in Voc with decreasing temperature down to 77 K, which suggests that the room-temperature operation is limited by non-radiative recombination. An open-circuit voltage of 1.22 V and an efficiency of 8.46 % is demonstrated at 77 K. It is expected that a coherently strained MgCdTe/CdTe/MgCdTe DH solar cell design will produce higher efficiency and Voc compared to the ZnTe/CdTe/MgCdTe design with relaxed ZnTe layer.
ContributorsDiNezza, Michael John (Author) / Zhang, Yong-Hang (Thesis advisor) / Johnson, Shane (Committee member) / Tao, Meng (Committee member) / Holman, Zachary (Committee member) / Arizona State University (Publisher)
Created2014
Description
This dissertation aims to demonstrate a new approach to fabricating solar cells for spectrum-splitting photovoltaic systems with the potential to reduce their cost and complexity of manufacturing, called Monolithically Integrated Laterally Arrayed Multiple Band gap (MILAMB) solar cells. Single crystal semiconductor alloy nanowire (NW) ensembles are grown with the alloy composition and band gap changing continuously across a broad range over the surface of a single substrate in a single, inexpensive growth step by the Dual-Gradient Method. The nanowire ensembles then serve as the absorbing materials in a set of solar cells for spectrum-splitting photovoltaic systems.
Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
ContributorsCaselli, Derek (Author) / Ning, Cun-Zheng (Thesis advisor) / Tao, Meng (Committee member) / Yu, Hongbin (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014
Description
In this work, a highly sensitive strain sensing technique is developed to realize in-plane strain mapping for microelectronic packages or emerging flexible or foldable devices, where mechanical or thermal strain is a major concern that could affect the performance of the working devices or even lead to the failure of the devices. Therefore strain sensing techniques to create a contour of the strain distribution is desired.
The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.
The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.
In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.
The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.
In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Poon, Poh Chieh Benny (Committee member) / Jiang, Hanqing (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
Description
In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET.
ContributorsAshraf, Nabil Shovon (Author) / Vasileska, Dragica (Thesis advisor) / Schroder, Dieter (Committee member) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
Dual-wavelength laser sources have various existing and potential applications in wavelength division multiplexing, differential techniques in spectroscopy for chemical sensing, multiple-wavelength interferometry, terahertz-wave generation, microelectromechanical systems, and microfluidic lab-on-chip systems. In the drive for ever smaller and increasingly mobile electronic devices, dual-wavelength coherent light output from a single semiconductor laser diode would enable further advances and deployment of these technologies. The output of conventional laser diodes is however limited to a single wavelength band with a few subsequent lasing modes depending on the device design. This thesis investigates a novel semiconductor laser device design with a single cavity waveguide capable of dual-wavelength laser output with large spectral separation. The novel dual-wavelength semiconductor laser diode uses two shorter- and longer-wavelength active regions that have separate electron and hole quasi-Fermi energy levels and carrier distributions. The shorter-wavelength active region is based on electrical injection as in conventional laser diodes, and the longer-wavelength active region is then pumped optically by the internal optical field of the shorter-wavelength laser mode, resulting in stable dual-wavelength laser emission at two different wavelengths quite far apart. Different designs of the device are studied using a theoretical model developed in this work to describe the internal optical pumping scheme. The carrier transport and separation of the quasi-Fermi distributions are then modeled using a software package that solves Poisson's equation and the continuity equations to simulate semiconductor devices. Three different designs are grown using molecular beam epitaxy, and broad-area-contact laser diodes are processed using conventional methods. The modeling and experimental results of the first generation design indicate that the optical confinement factor of the longer-wavelength active region is a critical element in realizing dual-wavelength laser output. The modeling predicts lower laser thresholds for the second and third generation designs; however, the experimental results of the second and third generation devices confirm challenges related to the epitaxial growth of the structures in eventually demonstrating dual-wavelength laser output.
ContributorsGreen, Benjamin C (Author) / Zhang, Yong-Hang (Thesis advisor) / Ning, Cun-Zheng (Committee member) / Tao, Nongjian (Committee member) / Roedel, Ronald J (Committee member) / Arizona State University (Publisher)
Created2011