Micromachining has seen application growth in a variety of industries requiring a miniaturization of the machining process. Machining at the micro level generates different cutter/workpiece interactions, generating more localized temperature spikes in the part/sample, as suggested by multiple studies. Temper-etch inspection is a non-destructive test used to identify `grind burns' or localized over-heating in steel components. This research investigated the application of temper-etch inspection to micromachined steel. The tests were performed on AISI 4340 steel samples. Finding, indications of localized over-heating was the primary focus of the experiment. In addition, change in condition between the original and post-machining hardness in the machined slot bottom was investigated. The results revealed that, under the conditions of the experiment, no indications of localized over-heating were present. However, there was a change in hardness at the bottom of the machined slot compared to the rest of the sample. Further research is needed to test the applicability of temper-etch inspection to micromilled steel and to identify the source of the change in hardness.

ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.

Ethernet switching is provided to interconnect multiple Ethernets for the exchange of Ethernet data frames. Most Ethernet switches require data buffering and Ethernet signal regeneration at the switch which incur the problems of substantial signal processing, power consumption, and transmission delay. To solve these problems, a cross bar architecture switching system for 10GBASE-T Ethernet is proposed in this thesis. The switching system is considered as the first step of implementing a multi-stage interconnection network to achieve Terabit or Petabit switching. By routing customized headers in capsulated Ethernet frames in an out-of-band control method, the proposed switching system would transmit the original Ethernet frames with little processing, thereby makes the system appear as a simple physical medium for different hosts. The switching system is designed and performed by using CMOS technology.

Market acceptability of distributed energy resource (DER) technologies and the gradual and consistent increase in their depth of penetration have generated significant interest over the past few years. In particular, in Arizona and several other states there has been a substantial in-crease in distributed photovoltaic (PV) generation interfaced to the power distribution systems, and is expected to continue to grow at a significant rate. This has made integration, control and optimal operation of DER units a main area of focus in the design and operation of distribution systems. Grid-connected, distributed PV covers a wide range of power levels ranging from small, single phase residential roof-top systems to large three-phase, multi-megawatt systems. The focus of this work is on analyzing large, three-phase systems, with the power distribution system of the Arizona State University (ASU) Tempe campus used as the test bed for analysis and simulation. The Tempe campus of ASU has presently 4.5 MW of installed PV capacity, with another 4.5 MW expected to be added by 2011, which will represent about 22% of PV penetration. The PV systems are interfaced to the grid invariably by a power electronic inverter. Many of the important characteristics of the PV generation are influenced by the design and performance of the inverter, and hence suitable models of the inverter are needed to analyze PV systems. Several models of distributed generation (DG), including switching and average models, suitable for different study objectives, and different control modes of the inverter have been described in this thesis. A critical function of the inverters is to quickly detect and eliminate unintentional islands during grid failure. In this thesis, many active anti-islanding techniques with voltage and frequency positive feedback have been studied. Effectiveness of these techniques in terms of the tripping times specified in IEEE Std. 1547 for interconnecting distributed resources with electric power systems has been analyzed. The impact of distributed PV on the voltage profile of a distribution system has been ana-lyzed with ASU system as the test bed using power systems analysis tools namely PowerWorld and CYMDIST. The present inverters complying with IEEE 1547 do not regulate the system vol-tage. However, the future inverters especially at higher power levels are expected to perform sev-eral grid support functions including voltage regulation and reactive power support. Hence, the impact of inverters with the reactive power support capabilities is also analyzed. Various test sce-narios corresponding to different grid conditions are simulated and it is shown that distributed PV improves the voltage profile of the system. The improvements are more significant when the PV generators are capable of reactive power support. Detailed short circuit analyses are also per-formed on the system, and the impact of distributed PV on the fault current magnitude, with and without reactive power injection, have been studied.

The RADiation sensitive Field Effect Transistor (RADFET) has been conventionally used to measure radiation dose levels. These dose sensors are calibrated in such a way that a shift in threshold voltage, due to a build-up of oxide-trapped charge, can be used to estimate the radiation dose. In order to estimate the radiation dose level using RADFET, a wired readout circuit is necessary. Using the same principle of oxide-trapped charge build-up, but by monitoring the change in capacitance instead of threshold voltage, a wireless dose sensor can be developed. This RADiation sensitive CAPacitor (RADCAP) mounted on a resonant patch antenna can then become a wireless dose sensor. From the resonant frequency, the capacitance can be extracted which can be mapped back to estimate the radiation dose level. The capacitor acts as both radiation dose sensor and resonator element in the passive antenna loop. Since the MOS capacitor is used in passive state, characterizing various parameters that affect the radiation sensitivity is essential. Oxide processing technique, choice of insulator material, and thickness of the insulator, critically affect the dose response of the sensor. A thicker oxide improves the radiation sensitivity but reduces the dynamic range of dose levels for which the sensor can be used. The oxide processing scheme primarily determines the interface trap charge and oxide-trapped charge development; controlling this parameter is critical to building a better dose sensor.

Photovoltaic (PV) modules appear to have three classifications of failure: Infant mortality, normal-life failure, and end-of-life failure. Little is known of the end-of-life failures experienced by PV modules due to their inherent longevity. Accelerated Life Testing (ALT) has been at the crux of this lifespan prediction; however, without naturally failing modules an accurate acceleration factor cannot be determined for use in ALT. By observing modules that have been aged in the field, a comparison can be made with modules undergoing accelerated testing. In this study an investigation on about 1900 aged (10-17 years) grid-tied PV modules installed in the desert climatic condition of Arizona was undertaken. The investigation was comprised of a check sheet that documented any visual defects and their severity, infrared (IR) scanning, and current-voltage (I-V) curve measurements. After data was collected on modules, an analysis was performed to classify the failure modes and to determine the annual performance degradation rates.

Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250&degC.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235&degC.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.

The U.S. Navy is interested in evaluating the dielectric performance of SF6 at 30 kHz in order to develop optimal bushing designs and to ensure reliable operation for the Very Low Frequency/ Low Frequency (VLF/LF) transmitting stations. The breakdown experiments of compressed SF6 at 30 kHz in the pressure range of 1-5 atm were conducted in both the uniform field (plane-plane gap) and the non-uniform field (rod-plane gap). To understand the impact of pressure on the breakdown voltage of SF6 at VLF/LF, empirical models of the dielectric strength of SF6 were derived based on the experimental data and regression analysis. The pressure correction factors that present the correlation between the breakdown voltage of SF6 at VLF/LF and that of air at 50/60 Hz were calculated. These empirical models provide an effective way to use the extensively documented breakdown voltage data of air at 60 Hz to evaluate the dielectric performance of SF6 for the design of VLF/LF high voltage equipment. In addition, several breakdown experiments and similar regression analysis of air at 30 kHz were conducted as well. A ratio of the breakdown voltage of SF6 to that of air at VLF/LF was calculated, from which a significant difference between the uniform gap and the non-uniform gap was observed. All the models and values provide useful information to evaluate and predict the performance of the bushings in practice.

There is a growing interest in the creation of three-dimensional (3D) images and videos due to the growing demand for 3D visual media in commercial markets. A possible solution to produce 3D media files is to convert existing 2D images and videos to 3D. The 2D to 3D conversion methods that estimate the depth map from 2D scenes for 3D reconstruction present an efficient approach to save on the cost of the coding, transmission and storage of 3D visual media in practical applications. Various 2D to 3D conversion methods based on depth maps have been developed using existing image and video processing techniques. The depth maps can be estimated either from a single 2D view or from multiple 2D views. This thesis presents a MATLAB-based 2D to 3D conversion system from multiple views based on the computation of a sparse depth map. The 2D to 3D conversion system is able to deal with the multiple views obtained from uncalibrated hand-held cameras without knowledge of the prior camera parameters or scene geometry. The implemented system consists of techniques for image feature detection and registration, two-view geometry estimation, projective 3D scene reconstruction and metric upgrade to reconstruct the 3D structures by means of a metric transformation. The implemented 2D to 3D conversion system is tested using different multi-view image sets. The obtained experimental results of reconstructed sparse depth maps of feature points in 3D scenes provide relative depth information of the objects. Sample ground-truth depth data points are used to calculate a scale factor in order to estimate the true depth by scaling the obtained relative depth information using the estimated scale factor. It was found out that the obtained reconstructed depth map is consistent with the ground-truth depth data.

Passive flow control achieved by surface dimpling can be an effective strategy for reducing drag around bluff bodies - an example of substantial popular interest being the flow around a golf ball. While the general effect of dimples causing a delay of boundary layer separation is well known, the mechanisms contributing to this phenomena are subtle and not thoroughly understood. Numerical models offer a powerful approach for studying drag reduction, however simulation strategies are challenged by complex geometries, and in applications the introduction of ad hoc turbulence models which introduce additional uncertainty. These and other factors provide much of the motivation for the current study, which focused on the numerical simulations of the flow over a simplified configuration consisting of a dimpled flat plate. The principal goals of the work are to understand the performance of the numerical methodology, and gain insight into the underlying physics of the flow. Direct numerical simulation of the incompressible Navier-Stokes equations using a fractional step method was employed, with the dimpled flat plate represented using an immersed boundary method. The dimple geometry utilizes a fixed dimple aspect ratio, with dimples arranged in a single spanwise row. The grid sizes considered ranged from approximately 3 to 99 million grid points. Reynolds numbers of 3000 and 4000 based on the inlet laminar boundary layer thickness were simulated. A turbulent boundary layer was induced downstream of the dimples for Reynolds numbers which did not transition for the flow over an undimpled flat plate. First and second order statistics of the boundary layer that develops agree reasonably well with those for turbulent channel flow and flat plate boundary layers in the sublayer and buffer layers, but differ in the outer layer. Inspection of flow visualizations suggest that early transition is promoted by thinning of the boundary layer, initiation of shear layer instabilities over the dimples, flow separation and reattachment, and tripping of the boundary layer at the trailing edge of the dimples.