Matching Items (21)
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- All Subjects: engineering
- All Subjects: Audio amplifiers--Design and construction.
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Sugar, Thomas
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
Brain Computer Interfaces are becoming the next generation controllers not only in the medical devices for disabled individuals but also in the gaming and entertainment industries. In order to build an effective Brain Computer Interface, which accurately translates the user thoughts into machine commands, it is important to have robust and fail proof signal processing and machine learning modules which operate on the raw EEG signals and estimate the current thought of the user.
In this thesis, several techniques used to perform EEG signal pre-processing, feature extraction and signal classification have been discussed, implemented, validated and verified; efficient supervised machine learning models, for the EEG motor imagery signal classification are identified. To further improve the performance of system unsupervised feature learning techniques have been investigated by pre-training the Deep Learning models. Use of pre-training stacked autoencoders have been proposed to solve the problems caused by random initialization of weights in neural networks.
Motor Imagery (imaginary hand and leg movements) signals are acquire using the Emotiv EEG headset. Different kinds of features like mean signal, band powers, RMS of the signal have been extracted and supplied to the machine learning (ML) stage, wherein, several ML techniques like LDA, KNN, SVM, Logistic regression and Neural Networks are applied and validated. During the validation phase the performances of various techniques are compared and some important observations are reported. Further, deep Learning techniques like autoencoding have been used to perform unsupervised feature learning. The reliability of the features is analyzed by performing classification by using the ML techniques mentioned earlier. The performance of the neural networks has been further improved by pre-training the network in an unsupervised fashion using stacked autoencoders and supplying the stacked autoencoders’ network parameters as initial parameters to the neural network. All the findings in this research, during each phase (pre-processing, feature extraction, classification) are directly relevant and can be used by the BCI research community for building motor imagery based BCI applications.
Additionally, this thesis attempts to develop, test, and compare the performance of an alternative method for classifying human driving behavior. This thesis proposes the use of driver affective states to know the driving behavior. The purpose of this part of the thesis was to classify the EEG data collected from several subjects while driving simulated vehicle and compare the classification results with those obtained by classifying the driving behavior using vehicle parameters collected simultaneously from all the subjects. The objective here is to see if the drivers’ mental state is reflected in his driving behavior.
In this thesis, several techniques used to perform EEG signal pre-processing, feature extraction and signal classification have been discussed, implemented, validated and verified; efficient supervised machine learning models, for the EEG motor imagery signal classification are identified. To further improve the performance of system unsupervised feature learning techniques have been investigated by pre-training the Deep Learning models. Use of pre-training stacked autoencoders have been proposed to solve the problems caused by random initialization of weights in neural networks.
Motor Imagery (imaginary hand and leg movements) signals are acquire using the Emotiv EEG headset. Different kinds of features like mean signal, band powers, RMS of the signal have been extracted and supplied to the machine learning (ML) stage, wherein, several ML techniques like LDA, KNN, SVM, Logistic regression and Neural Networks are applied and validated. During the validation phase the performances of various techniques are compared and some important observations are reported. Further, deep Learning techniques like autoencoding have been used to perform unsupervised feature learning. The reliability of the features is analyzed by performing classification by using the ML techniques mentioned earlier. The performance of the neural networks has been further improved by pre-training the network in an unsupervised fashion using stacked autoencoders and supplying the stacked autoencoders’ network parameters as initial parameters to the neural network. All the findings in this research, during each phase (pre-processing, feature extraction, classification) are directly relevant and can be used by the BCI research community for building motor imagery based BCI applications.
Additionally, this thesis attempts to develop, test, and compare the performance of an alternative method for classifying human driving behavior. This thesis proposes the use of driver affective states to know the driving behavior. The purpose of this part of the thesis was to classify the EEG data collected from several subjects while driving simulated vehicle and compare the classification results with those obtained by classifying the driving behavior using vehicle parameters collected simultaneously from all the subjects. The objective here is to see if the drivers’ mental state is reflected in his driving behavior.
ContributorsManchala, Vamsi Krishna (Author) / Redkar, Sangram (Thesis advisor) / Rogers, Bradley (Committee member) / Sugar, Thomas (Committee member) / Arizona State University (Publisher)
Created2015
Description
The sensor industry is a growing industry that has been predicted by Allied Market Research to be a multi-billion industry by 2022. One of the many key drives behind this rapid growth in the sensor industry is the increase incorporation of sensors into portable electrical devices. The value for sensor technologies are increased when the sensors are developed into innovative measuring system for application uses in the Aerospace, Defense, and Healthcare industries. While sensors are not new, their increased performance, size reduction, and decrease in cost has opened the door for innovative sensor combination for portable devices that could be worn or easily moved around. With this opportunity for further development of sensor use through concept engineering development, three concept projects for possible innovative portable devices was undertaken in this research. One project was the development of a pulse oximeter devise with fingerprint recognition. The second project was prototyping a portable Bluetooth strain gage monitoring system. The third project involved sensors being incorporated onto flexible printed circuit board (PCB) for improved comfort of wearable devices. All these systems were successfully tested in lab.
ContributorsNichols, Kevin William (Author) / Redkar, Sangram (Thesis advisor) / Rogers, Brad (Committee member) / Sugar, Thomas (Committee member) / Arizona State University (Publisher)
Created2018
Description
Recent research and study have showed the potential of auto-parametric system in controlling stability and parametric resonance. In this project, two different designs for auto-parametrically excited mass-spring-damper systems were studied. The theoretical models were developed to describe the behavior of the systems, and simulation models were constructed to validate the analytical results. The error between simulation and theoretical results was within 2%. Both theoretical and simulation results showed that the implementation of auto-parametric system could help reduce or amplify the resonance significantly.
ContributorsLe, Thao (Author) / Redkar, Sangram (Thesis advisor) / Sugar, Thomas (Committee member) / Rogers, Brad (Committee member) / Arizona State University (Publisher)
Created2018
Description
A control method based on the phase angle is used to control oscillating systems. The phase oscillator uses the sine and cosine of the phase angle to change key properties of a mass-spring-damper system, including amplitude, frequency, and equilibrium. An inverted pendulum is used to show a further application of the phase oscillator. Two methods of control based on the phase oscillator are used for swing-up and balancing of the pendulum. The first control method involves two separate stages. The scenarios where this control works are discussed. The second control method uses variable coefficients to result in a smooth transition between swing-up and balancing.
ContributorsBates, Andrew (Author) / Sugar, Thomas (Thesis advisor) / Redkar, Sangram (Committee member) / Mignolet, Marc (Committee member) / Arizona State University (Publisher)
Created2015
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
In this thesis, a digital input class D audio amplifier system which has the ability
to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.
Based on simulation, the power supply rejection at 200Hz is about -49dB with
81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.
Based on simulation, the power supply rejection at 200Hz is about -49dB with
81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
ContributorsBai, Jing (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2015