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Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.
ContributorsHabibiMehr, Payam (Author) / Thornton, Trevor John (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Formicone, Gabriele (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2019
Description
The Phoenix CubeSat is a 3U Earth imaging CubeSat which will take infrared (IR) photos of cities in the United Stated to study the Urban Heat Island Effect, (UHI) from low earth orbit (LEO). It has many different components that need to be powered during the life of its mission. The only power source during the mission will be its solar panels. It is difficult to calculate power generation from solar panels by hand because of the different orientations the satellite will be positioned in during orbit; therefore, simulation will be used to produce power generation data. Knowing how much power is generated is integral to balancing the power budget, confirming whether there is enough power for all the components, and knowing whether there will be enough power in the batteries during eclipse. This data will be used to create an optimal design for the Phoenix CubeSat to accomplish its mission.
ContributorsBarakat, Raymond John (Author) / White, Daniel (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2017-05
Description
Current technology does not allow for the full amount of power produced by solar arrays (PV) on spacecraft to be utilized. The arrays are designed with non-reconfigurable architectures and sent on fifteen to twenty year long missions. They cannot be changed once they are in space, so the arrays are designed for the end of life. Throughout their lifetime, solar arrays can degrade in power producing capabilities anywhere from 20% to 50%. Because there is such a drastic difference in the beginning and end of life power production, and because they cannot be reconfigured, a new design has been found necessary in order to increase power production. Reconfiguration allows the solar arrays to achieve maximum power producing capabilities at both the beginning and end of their lives. With the potential to increase power production by 50%, the reconfiguration design consists of a switching network to be able to utilize any combination of cells. The design for reconfiguration must meet the power requirements of the solar array. This thesis will explore different designs for reconfiguration, as well as possible switches for implementation. It will also review other methods to increase power production, as well as discuss future work in this field.
ContributorsJohnson, Everett Hope (Author) / Kitchen, Jennifer (Thesis director) / Ozev, Sule (Committee member) / School of International Letters and Cultures (Contributor) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
In this paper, we propose an autonomous throwing and catching system to be developed as a preliminary step towards the refinement of a robotic arm capable of improving strength and motor function in the limb. This will be accomplished by first autonomizing simpler movements, such as throwing a ball. In this system, an autonomous thrower will detect a desired target through the use of image processing. The launch angle and direction necessary to hit the target will then be calculated, followed by the launching of the ball. The smart catcher will then detect the ball as it is in the air, calculate its expected landing location based on its initial trajectory, and adjust its position so that the ball lands in the center of the target. The thrower will then proceed to compare the actual landing position with the position where it expected the ball to land, and adjust its calculations accordingly for the next throw. By utilizing this method of feedback, the throwing arm will be able to automatically correct itself. This means that the thrower will ideally be able to hit the target exactly in the center within a few throws, regardless of any additional uncertainty in the system. This project will focus of the controller and image processing components necessary for the autonomous throwing arm to be able to detect the position of the target at which it will be aiming, and for the smart catcher to be able to detect the position of the projectile and estimate its final landing position by tracking its current trajectory.
ContributorsLundberg, Kathie Joy (Co-author) / Thart, Amanda (Co-author) / Rodriguez, Armando (Thesis director) / Berman, Spring (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
This project examines the science of electric field sensing and completes experiments, gathering data to support its utility for various applications. The basic system consists of a transmitter, receiver, and lock-in amplifier. The primary goal of the study was to determine if such a system could detect a human disturbance, due to the capacitance of a human body, and such a thesis was supported. Much different results were obtained when a person disturbed the electric field transmitted by the system than when other types of objects, such as chairs and electronic devices, were placed in the field. In fact, there was a distinct difference between persons of varied sizes as well. This thesis goes through the basic design of the system and the process of experimental design for determining the capabilities of such an electric field sensing system.
ContributorsBranham, Breana Michelle (Author) / Allee, David (Thesis director) / Papandreou-Suppappola, Antonia (Committee member) / Phillips, Stephen (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / School of International Letters and Cultures (Contributor)
Created2013-05
Description
A hybrid PV/T module was built, consisting of a thermal liquid heating system and a photovoltaic module system that combine in a hybrid format. This report will discuss the work on the project from Fall 2012 to Spring 2013 and the extended section on the economics for the Honors Thesis. Three stages of experiments were completed. Stage 1 showed our project was functional as we were able to verify our panel produced electricity and increased the temperature of water flowing in the system by 0.65°C. Stage 2 testing included “gluing” the flow system to the back of the panel resulting in an average increase of 4.76°C in the temperature of the water in the system. Stage 3 testing included adding insulating foam to the module which resulted in increasing the average temperature of the water in our flow system by 6.95°C. The economic calculations show the expected energy cost savings for Arizona residents.
ContributorsHaines, Brent Robert (Author) / Roedel, Ronald (Thesis director) / Aberle, James (Committee member) / Rauch, Dawson (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2013-05
Description
With the progression of different industries moving away from employing secretaries for business professionals and professors, there exists a void in the area of personal assistance. This problem has existing solutions readily available to replace this service, i.e. secretary or personal assistant, tend to range from expensive and useful to inexpensive and not efficient. This leaves a low cost niche into the market of a virtual office assistant or manager to display messages and to help direct people in obtaining contact information. The development of a low cost solution revolves around the software needed to solve the various problems an accessible and user friendly Virtual Interface in which the owner of the Virtual Office Manager/Assistant can communicate to colleagues who are at standby outside of the owner's office and vice versa. This interface will be allowing the owner to describe the status pertaining to their absence or any other message sent to the interface. For example, the status of the owner's work commute can be described with a simple "Running Late" phrase or a message like "Busy come back in 10 minutes". In addition, any individual with an interest to these entries will have the opportunity to respond back because the device will provide contact information. When idle, the device will show supplemental information such as the owner's calendar and name. The scope of this will be the development and testing of solutions to achieve these goals.
ContributorsOffenberger, Spencer Eliot (Author) / Kozicki, Michael (Thesis director) / Goryll, Michael (Committee member) / Electrical Engineering Program (Contributor) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
Since the inception of Internet of Things (IoT) framework, the amount of interaction between electronic devices has tremendously increased and the ease of implementing software between such devices has bettered. Such data exchange between devices, whether between Node to Server or Node to Node, has paved way for creating new business models. Wireless Video Sensor Network Platforms are being used to monitor and understand the surroundings better. Both hardware and software supporting such devices have become much smaller and yet stronger to enable these. Specifically, the invention of better software that enable Wireless data transfer have become more simpler and lightweight technologies such as HTML5 for video rendering, Common Gateway Interface(CGI) scripts enabling interactions between client and server and WebRTC from Google for peer to peer interactions. The role of web browsers in enabling these has been vastly increasing.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
ContributorsRentala, Sri Harsha (Author) / Reisslein, Martin (Thesis advisor) / Kitchen, Jennifer (Committee member) / McGarry, Michael (Committee member) / Arizona State University (Publisher)
Created2016