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Description
Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary

Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supply
ContributorsKundur, Vinay (Author) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
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Description
The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured

The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to develop different methodologies. At present, MEMS devices are tested using mechanical stimuli to measure the device parameters and for calibration the device. This testing is necessary since the MEMS process is not a very well controlled process unlike CMOS. This is done using an ATE and the cost of using ATE (automatic testing equipment) contribute to 30-40% of the devices final cost. This thesis proposes an architecture which can use an Electrical Signal to stimulate the MEMS device and use the data from the MEMS response in approximating the calibration coefficients efficiently. As a proof of concept, we have designed a BIST (Built-in self-test) circuit for MEMS accelerometer. The BIST has an electrical stimulus generator, Capacitance-to-voltage converter, ∑ ∆ ADC. This thesis explains in detail the design of the Electrical stimulus generator. We have also designed a technique to correlate the parameters obtained from electrical stimuli to those obtained by mechanical stimuli. This method is cost effective since the additional circuitry needed to implement BIST is less since the technique utilizes most of the existing standard readout circuitry already present.
ContributorsJangala Naga, Naveen Sai (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased

Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
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Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices

ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly

Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process

Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.

This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
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Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to

The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.

The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
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Description
In this thesis, a digital input class D audio amplifier system which has the ability

to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress

In this thesis, a digital input class D audio amplifier system which has the ability

to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.

Based on simulation, the power supply rejection at 200Hz is about -49dB with

81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
ContributorsBai, Jing (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2015
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Description
This thesis presents a power harvesting system combining energy from sub-cells of

multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost

converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current

regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A

modified hill-climbing algorithm is implemented to achieve maximum

This thesis presents a power harvesting system combining energy from sub-cells of

multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost

converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current

regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A

modified hill-climbing algorithm is implemented to achieve maximum power point

tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V

output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of

65mW. Measured results show that the peak efficiency achieved is around 85%. The

power switches and control circuits are implemented in standard 0.18um CMOS process.
ContributorsPeng, Qirong (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
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Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change

The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013