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- Genre: Doctoral Dissertation
- Creators: Alford, Terry
Description
This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20µm - 200µm, fine traces with varying widths of 3µm - 30µm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show “smart” control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry.
ContributorsGanesan, Kousik (Author) / Tasooji, Amaneh (Thesis advisor) / Manepalli, Rahul (Committee member) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2018
Description
An ongoing effort in the photovoltaic (PV) industry is to reduce the major manufacturing cost components of solar cells, the great majority of which are based on crystalline silicon (c-Si). This includes the substitution of screenprinted silver (Ag) cell contacts with alternative copper (Cu)-based contacts, usually applied with plating. Plated Cu contact schemes have been under study for many years with only minor traction in industrial production. One of the more commonly-cited barriers to the adoption of Cu-based contacts for photovoltaics is long-term reliability, as Cu is a significant contaminant in c-Si, forming precipitates that degrade performance via degradation of diode character and reduction of minority carrier lifetime. Cu contamination from contacts might cause degradation during field deployment if Cu is able to ingress into c-Si. Furthermore, Cu contamination is also known to cause a form of light-induced degradation (LID) which further degrades carrier lifetime when cells are exposed to light.
Prior literature on Cu-contact reliability tended to focus on accelerated testing at the cell and wafer level that may not be entirely replicative of real-world environmental stresses in PV modules. This thesis is aimed at advancing the understanding of Cu-contact reliability from the perspective of quasi-commercial modules under more realistic stresses. In this thesis, c-Si solar cells with Cu-plated contacts are fabricated, made into PV modules, and subjected to environmental stress in an attempt to induce hypothesized failure modes and understand any new vulnerabilities that Cu contacts might introduce. In particular, damp heat stress is applied to conventional, p-type c-Si modules and high efficiency, n-type c-Si heterojunction modules. I present evidence of Cu-induced diode degradation that also depends on PV module materials, as well as degradation unrelated to Cu, and in either case suggest engineering solutions to the observed degradation. In a forensic search for degradation mechanisms, I present novel evidence of Cu outdiffusion from contact layers and encapsulant-driven contact corrosion as potential key factors. Finally, outdoor exposures to light uncover peculiarities in Cu-plated samples, but do not point to especially serious vulnerabilities.
Prior literature on Cu-contact reliability tended to focus on accelerated testing at the cell and wafer level that may not be entirely replicative of real-world environmental stresses in PV modules. This thesis is aimed at advancing the understanding of Cu-contact reliability from the perspective of quasi-commercial modules under more realistic stresses. In this thesis, c-Si solar cells with Cu-plated contacts are fabricated, made into PV modules, and subjected to environmental stress in an attempt to induce hypothesized failure modes and understand any new vulnerabilities that Cu contacts might introduce. In particular, damp heat stress is applied to conventional, p-type c-Si modules and high efficiency, n-type c-Si heterojunction modules. I present evidence of Cu-induced diode degradation that also depends on PV module materials, as well as degradation unrelated to Cu, and in either case suggest engineering solutions to the observed degradation. In a forensic search for degradation mechanisms, I present novel evidence of Cu outdiffusion from contact layers and encapsulant-driven contact corrosion as potential key factors. Finally, outdoor exposures to light uncover peculiarities in Cu-plated samples, but do not point to especially serious vulnerabilities.
ContributorsKaras, Joseph (Author) / Bowden, Stuart (Thesis advisor) / Alford, Terry (Thesis advisor) / Tamizhmani, Govindasamy (Committee member) / Michaelson, Lynne (Committee member) / Arizona State University (Publisher)
Created2020