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201136 https://hdl.handle.net/2286/R.2.N.201136 http://rightsstatements.org/vocab/InC/1.0/ All Rights Reserved 2025 130 pages Doctoral Dissertation Academic theses en Bhanushali, Sumukh Prashant Sanyal, Arindam Bakkaloglu, Bertan Garrity, Douglas Pagano, Rosario Arizona State University Partial requirement for: Ph.D., Arizona State University, 2025 Field of study: Electrical Engineering Data converters serve as the boundary between the analog real world and digital computing devices, where information is captured, processed, and stored. Analog-to- Digital Converters (ADCs) are key components enabling technologies across domains, from physics to communication. These applications demand ADCs with high resolution, speed, and energy efficiency. Technology scaling has improved ADC energy efficiency by reducing supply voltages, but it also introduces challenges. While smaller process nodes offer higher speed and efficiency, they reduce intrinsic gain and voltage headroom, making traditional analog circuit design more challenging. Additionally, smaller geometries lead to higher static and dynamic errors. Combined with stringent bandwidth and resolution requirements, these non-idealities make ADC design increasingly difficult. To address these challenges, ADC designs are shifting toward highly digital architectures that avoid the limitations of traditional analog approaches. This work follows this trend by leveraging digital-intensive techniques to enhance ADC performance. In high-resolution ADCs, a Noise-Shaping Successive Approximation Register (NS-SAR) combined with a Voltage-Controlled Oscillator (VCO)-based ADC improves energy efficiency while benefiting from the highly digital nature of the VCO. This approach has been validated through two prototypes in 65nm CMOS. For high-frequency (HF) applications, SAR ADCs are commonly used in Time- Interleaved (TI) or pipelined ADC architectures due to their accessible residue and energy efficiency. However, SAR ADCs suffer from errors such as reference ripple, comparator kickback, and capacitor mismatch. Traditional methods target specific error sources, but this thesis proposes a machine learning-based approach to mitigate both static and dynamic errors without prior knowledge. Since these errors are deterministic, comparing the ADC’s output with an ideal ADC allows for error pattern recognition. This ML-based method utilizes a low frequency reference ADC, which shares the same input as the HF ADC but is free from HF-related errors. The reference ADC provides ground truth for the ML model, enabling it to learn and correct errors in the HF ADC. Electrical Engineering Engineering Physics Analog to digital converter Delta-sigma modulators Integrated circuits Machine learning Noise shaping Successive approximation register Improving SAR ADC Performance with Scaling Friendly Solutions