2026-05-20T10:01:45Zhttps://keep.lib.asu.edu/oai/request

oai:keep.lib.asu.edu:node-2011332025-05-05T15:53:02Zoai_pmh:repo_items

201133 https://hdl.handle.net/2286/R.2.N.201133 http://rightsstatements.org/vocab/InC/1.0/ All Rights Reserved 2025 2027-05-01T10:55:59 136 pages Doctoral Dissertation Academic theses en Nayak, Rakshit Dambe Bakkaloglu, Bertan Garrity, Douglas Kitchen, Jennifer Sanyal, Arindam Arizona State University Partial requirement for: Ph.D., Arizona State University, 2025 Field of study: Electrical Engineering Recent advancements in technology with connected devices have increased the demand for developing compact battery-operated systems with integrated power management units. To increase the battery life of these systems, high efficiency and reliable power converters are required. One of the primary concerns in the design of switched capacitor (SC) DC-DC converters is its load-dependent output voltage ripple. An all-digital control technique to reduce the output ripple of fully integrated SC converters for ultralow-power applications is presented. The proposed ripple reduction loop (RRL) uses a two-step coarse-fine tuning approach by modulating the flying-capacitance and switch on-resistance respectively. The proposed method is adaptive to load changes and can operate from no-load up to 250μA full load. A 2:1 step down ratio SC converter with the proposed adaptive RRL is designed and fabricated in 180nm technology. Characterization results show that when the RRL is enabled, the output voltage ripple reduces from 45.6mV to 16.5mV for VOUT = 800mV and IOUT = 100μA, closely matching the mathematical model. The converter occupies a die area of 0.606mm2 including the flying-capacitor and output capacitor and achieves a peak efficiency of 70.49%.Another significant challenge for today’s power management circuits is the need for high efficiency and fast transient response over a wide range of operating conditions without significant increase in cost. A low Iq and low silicon area buck converter with current mode delay based hysteretic converter and a no load Iq=5.17μA is presented. A novel ring oscillator-based delay generation method is proposed for creating the hysteresis window enabling easy implementation and integration into frequency synchronization loop. The proposed converter operates at a constant switching frequency of 2.2MHz and supports a wide range of COUT. The design is implemented with power gating for analog blocks to reduce the static power dissipation in low power mode. The converter is implemented in 180nm technology and operates over a range of VIN = 3.5V-5.5V generating VOUT = 0.9V-2.4V. The converter is designed to supply max IOUT = 3A. The converter achieves a peak efficiency of 93.01% and maintains efficiency above 70% across all load conditions. Electrical Engineering dc dc converter hysteretic buck converter Low-Power ripple reduction switched capacitor converter Ripple Reduction Technique for Single Stage Switched Capacitor Converters and Delay Mode Hysteretic Buck Converter