2026-05-24T16:14:38Zhttps://keep.lib.asu.edu/oai/requestoai:keep.lib.asu.edu:node-1981562024-12-23T18:01:48Zoai_pmh:alloai_pmh:repo_items198156
https://hdl.handle.net/2286/R.2.N.198156
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2024
66 pages
Masters Thesis
Academic theses
Text
eng
Srikanth, Akshaya
Bliss, Daniel
Chakrabarti, Chaitali
Michelusi, Nicolò
Arizona State University
Partial requirement for: M.S., Arizona State University, 2024
Field of study: Computer Engineering
Interpolation is a crucial technique in signal processing that goes well beyond its conventional use in audio and image processing. Linear interpolation is a type of interpolation that is a simple method of estimating a value between two known points by assuming a straight-line relationship between them. Its applications are spread over various domains, including channel estimation, Doppler shift estimation, synthetic aperture radar (SAR), pulse compression, adaptive filtering, and radar and sonar signal processing.Domain Adaptive Processor (DAP) is a systolic array processor, developed by researchers at the University of Michigan to meet the needs of signal processing workloads. It consists of 64 Processing Elements (PEs) connected in a 2D array. Each PE is subdivided into smaller units (sub-PEs), which can load, store, and carry out mathematical operations for both real and complex numbers, making DAP globally homogeneous and locally heterogeneous.
The hardware code for DAP implementation was configured using a combination of handwritten Comma Separated Values (.csv) files and an auto-code generation tool. Researchers at ASU developed this tool to manage instruction redundancies and implement instruction-level parallelism for generating Very Long Instruction Word (VLIW) code for the DAP.
The thesis presents implementations, a single PE version and a multi PE version of linear interpolation. Each of them was evaluated and compared based on their latencies
Electrical Engineering
Domain Adaptive Processor
Domain Specific SoCs
Linear Interpolation
Processing Elements (PE)
Systolic Array Architecture
Verilog coding
Efficient Implementation of Interpolation on Domain Adaptive Processor