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197733 https://hdl.handle.net/2286/R.2.N.197733 http://rightsstatements.org/vocab/InC/1.0/ All Rights Reserved 2024 65 pages Doctoral Dissertation Academic theses Text eng Lu, Yuhong Bakkaloglu, Bertan BB Kitchen, Jennifer JK Sanyal, Arindam AS Magod, Raveesh RM Arizona State University Partial requirement for: Ph.D., Arizona State University, 2024 Field of study: Electrical Engineering Portable electronic devices are becoming an indispensable part of life. Systems-on-chip (SoC) ICs play a fundamental role in the design and functionality of portable devices. Multiple different voltage levels are required to power various components within the chip. Typically, switching regulators provide high-efficiency voltage supplies, while LDOs are cascoded after those switching regulators to offer clean power for the downstream circuitries. Accordingly, A high power supply rejection ratio (PSRR) at the mid-to-high frequency band (0.1-10 MHz) is crucial for generating a low-noise power supply. Moreover, portable devices demand a high-power efficiency low-dropout regulator (LDO) that provides lower dropout voltage, higher load current, and low quiescent current. However, it presents a significant challenge in enhancing the PSRR since the pass field effect transistor (FET) operates in the deep triode region at those conditions. Thus, an approach is required to improve PSRR regardless of the operation region of the pass FET.This work presents a parallel feed-forward current ripple rejection (PFFCRR) approach to improve the PSRR performance at both the saturation and triode regions of the NMOS pass FET. The proposed approach senses the supply-induced current ripple and cancels the original ripple through a current path that runs parallel to the NMOS pass FET. The proposed LDO is fabricated in a 180 nm BCD process. The proposed LDO achieves a PSRR better than -35 dB up to 10 MHz at 300 mV dropout voltage with 0.5 A load current and a load capacitor of 2.2 µF. The PFFCRR approach achieves a PSRR improvement of 18 dB at 1 MHz at 100 mV dropout voltage with a 2.15 A load current when the pass FET operates in the deep triode region. Moreover, the proposed LDO achieves an enhanced transient performance with an overshoot and undershoot of 40.54 mV and 36.45 mV, respectively, against ∆ILOAD of 1 A with a slew rate of 1 A/µs. Electrical Engineering deep triode region high power supply rejection ratio (PSRR) low-dropout regulator (LDO) parallel feed-forward current ripple rejection (PFFCRR) A Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR NMOS LDOs