2026-05-24T16:20:58Zhttps://keep.lib.asu.edu/oai/requestoai:keep.lib.asu.edu:node-1569622024-12-20T18:25:12Zoai_pmh:alloai_pmh:repo_items156962
https://hdl.handle.net/2286/R.I.51737
http://rightsstatements.org/vocab/InC/1.0/
2018
79 pages
Masters Thesis
Academic theses
Text
eng
Animesh, Saurabh
Chakrabarti, Chaitali
Brunhaver, John
Ren, Fengbo
Arizona State University
Masters Thesis Computer Engineering 2018
With the end of Dennard scaling and Moore's law, architects have moved towards<br/><br/>heterogeneous designs consisting of specialized cores to achieve higher performance<br/><br/>and energy efficiency for a target application domain. Applications of linear algebra<br/><br/>are ubiquitous in the field of scientific computing, machine learning, statistics,<br/><br/>etc. with matrix computations being fundamental to these linear algebra based solutions.<br/><br/>Design of multiple dense (or sparse) matrix computation routines on the<br/><br/>same platform is quite challenging. Added to the complexity is the fact that dense<br/><br/>and sparse matrix computations have large differences in their storage and access<br/><br/>patterns and are difficult to optimize on the same architecture. This thesis addresses<br/><br/>this challenge and introduces a reconfigurable accelerator that supports both dense<br/><br/>and sparse matrix computations efficiently.<br/><br/>The reconfigurable architecture has been optimized to execute the following linear<br/><br/>algebra routines: GEMV (Dense General Matrix Vector Multiplication), GEMM<br/><br/>(Dense General Matrix Matrix Multiplication), TRSM (Triangular Matrix Solver),<br/><br/>LU Decomposition, Matrix Inverse, SpMV (Sparse Matrix Vector Multiplication),<br/><br/>SpMM (Sparse Matrix Matrix Multiplication). It is a multicore architecture where<br/><br/>each core consists of a 2D array of processing elements (PE).<br/><br/>The 2D array of PEs is of size 4x4 and is scheduled to perform 4x4 sized matrix<br/><br/>updates efficiently. A sequence of such updates is used to solve a larger problem inside<br/><br/>a core. A novel partitioned block compressed sparse data structure (PBCSC/PBCSR)<br/><br/>is used to perform sparse kernel updates. Scalable partitioning and mapping schemes<br/><br/>are presented that map input matrices of any given size to the multicore architecture.<br/><br/>Design trade-offs related to the PE array dimension, size of local memory inside a core<br/><br/>and the bandwidth between on-chip memories and the cores have been presented. An<br/><br/>optimal core configuration is developed from this analysis. Synthesis results using a 7nm PDK show that the proposed accelerator can achieve a performance of upto<br/><br/>32 GOPS using a single core.
Electrical Engineering
Accelerator
Algebras, Linear
matrix
Multicore
Reconfigurable
sparse
Algorithm Architecture Co-design for Dense and Sparse Matrix Computations