2026-05-25T04:10:21Zhttps://keep.lib.asu.edu/oai/requestoai:keep.lib.asu.edu:node-1556312024-12-20T18:25:12Zoai_pmh:alloai_pmh:repo_items155631
https://hdl.handle.net/2286/R.I.44286
http://rightsstatements.org/vocab/InC/1.0/
All Rights Reserved
2017
66 pages
Masters Thesis
Academic theses
Text
eng
Gunavelu Mohan, Aswin
Sohoni, Sohum
Ren, Fengbo
Seo, Jae-Sun
Arizona State University
Masters Thesis Electrical Engineering 2017
The information era has brought about many technological advancements in the past<br/><br/>few decades, and that has led to an exponential increase in the creation of digital images and<br/><br/>videos. Constantly, all digital images go through some image processing algorithm for<br/><br/>various reasons like compression, transmission, storage, etc. There is data loss during this<br/><br/>process which leaves us with a degraded image. Hence, to ensure minimal degradation of<br/><br/>images, the requirement for quality assessment has become mandatory. Image Quality<br/><br/>Assessment (IQA) has been researched and developed over the last several decades to<br/><br/>predict the quality score in a manner that agrees with human judgments of quality. Modern<br/><br/>image quality assessment (IQA) algorithms are quite effective at prediction accuracy, and<br/><br/>their development has not focused on improving computational performance. The existing<br/><br/>serial implementation requires a relatively large run-time on the order of seconds for a single<br/><br/>frame. Hardware acceleration using Field programmable gate arrays (FPGAs) provides<br/><br/>reconfigurable computing fabric that can be tailored for a broad range of applications.<br/><br/>Usually, programming FPGAs has required expertise in hardware descriptive languages<br/><br/>(HDLs) or high-level synthesis (HLS) tool. OpenCL is an open standard for cross-platform,<br/><br/>parallel programming of heterogeneous systems along with Altera OpenCL SDK, enabling<br/><br/>developers to use FPGA's potential without extensive hardware knowledge. Hence, this<br/><br/>thesis focuses on accelerating the computationally intensive part of the most apparent<br/><br/>distortion (MAD) algorithm on FPGA using OpenCL. The results are compared with CPU<br/><br/>implementation to evaluate performance and efficiency gains.
Electrical Engineering
Computer Engineering
FPGA
Hardware Acceleration
Image Quality Assessment
OpenCL
Hardware Acceleration of Most Apparent Distortion Image Quality Assessment Algorithm on FPGA Using OpenCL