2026-05-25T21:20:48Zhttps://keep.lib.asu.edu/oai/requestoai:keep.lib.asu.edu:node-1550582024-12-20T18:25:12Zoai_pmh:alloai_pmh:repo_items155058
https://hdl.handle.net/2286/R.I.40738
http://rightsstatements.org/vocab/InC/1.0/
All Rights Reserved
2016
vi, 30 pages : illustrations (some color)
Masters Thesis
Academic theses
Text
eng
Dave, Shail
Shrivastava, Aviral
Ren, Fengbo
Ogras, Umit Y.
Arizona State University
Partial requirement for: M.S., Arizona State University, 2016
Includes bibliographical references (pages 28-30)
Field of study: Computer science
Coarse-grained Reconfigurable Arrays (CGRAs) are promising accelerators capable<br/><br/>of accelerating even non-parallel loops and loops with low trip-counts. One challenge<br/><br/>in compiling for CGRAs is to manage both recurring and nonrecurring variables in<br/><br/>the register file (RF) of the CGRA. Although prior works have managed recurring<br/><br/>variables via rotating RF, they access the nonrecurring variables through either a<br/><br/>global RF or from a constant memory. The former does not scale well, and the latter<br/><br/>degrades the mapping quality. This work proposes a hardware-software codesign<br/><br/>approach in order to manage all the variables in a local nonrotating RF. Hardware<br/><br/>provides modulo addition based indexing mechanism to enable correct addressing<br/><br/>of recurring variables in a nonrotating RF. The compiler determines the number of<br/><br/>registers required for each recurring variable and configures the boundary between the<br/><br/>registers used for recurring and nonrecurring variables. The compiler also pre-loads<br/><br/>the read-only variables and constants into the local registers in the prologue of the<br/><br/>schedule. Synthesis and place-and-route results of the previous and the proposed RF<br/><br/>design show that proposed solution achieves 17% better cycle time. Experiments of<br/><br/>mapping several important and performance-critical loops collected from MiBench<br/><br/>show proposed approach improves performance (through better mapping) by 18%,<br/><br/>compared to using constant memory.
Computer Engineering
Computer Science
Electrical Engineering
Accelerators
Coarse Grained Reconfigurable Array
compiler
Hardware-Software Co-design
Register File
Scalability
Computer architecture
Compilers (Computer programs)
Microprocessors
Scalable register file architecture for CGRA accelerators