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153033 https://hdl.handle.net/2286/R.I.26802 http://rightsstatements.org/vocab/InC/1.0/ All Rights Reserved 2014 vii, 38 p. : ill. (some col.) Masters Thesis Academic theses Text eng Rajendran Radhika, Shri Hari Shrivastava, Aviral Christen, Jennifer Blain Cao, Yu Arizona State University Partial requirement for: M.S., Arizona State University, 2014 Includes bibliographical references (p. 35-38) Field of study: Electrical engineering Coarse Grain Reconfigurable Arrays (CGRAs) are promising accelerators capable of<br/><br/>achieving high performance at low power consumption. While CGRAs can efficiently<br/><br/>accelerate loop kernels, accelerating loops with control flow (loops with if-then-else<br/><br/>structures) is quite challenging. Techniques that handle control flow execution in<br/><br/>CGRAs generally use predication. Such techniques execute both branches of an<br/><br/>if-then-else structure and select outcome of either branch to commit based on the<br/><br/>result of the conditional. This results in poor utilization of CGRA s computational<br/><br/>resources. Dual-issue scheme which is the state of the art technique for control flow<br/><br/>fetches instructions from both paths of the branch and selects one to execute at<br/><br/>runtime based on the result of the conditional. This technique has an overhead in<br/><br/>instruction fetch bandwidth. In this thesis, to improve performance of control flow<br/><br/>execution in CGRAs, I propose a solution in which the result of the conditional<br/><br/>expression that decides the branch outcome is communicated to the instruction fetch<br/><br/>unit to selectively issue instructions from the path taken by the branch at run time.<br/><br/>Experimental results show that my solution can achieve 34.6% better performance<br/><br/>and 52.1% improvement in energy efficiency on an average compared to state of the<br/><br/>art dual issue scheme without imposing any overhead in instruction fetch bandwidth. Electrical Engineering Computer Engineering Computer Science Coarse Grain Reconfigurable Arrays compilers Control flow energy efficient High Performance Microarchitecture Adaptive computing systems Computer architecture Path selection based branching for coarse grained reconfigurable arrays