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150460 https://hdl.handle.net/2286/R.I.14483 http://rightsstatements.org/vocab/InC/1.0/ All Rights Reserved 2011 xiii, 68 p. : col. ill Masters Thesis Academic theses Text eng Pager, Jared Shrivastava, Aviral Gupta, Sandeep Speyer, Gil Arizona State University Partial requirement for: M.S., Arizona State University, 2011 Includes bibliographical references (p. 65-68) Field of study: Computer science Performance improvements have largely followed Moore's Law due to the help from technology scaling. In order to continue improving performance, power-efficiency must be reduced. Better technology has improved power-efficiency, but this has a limit. Multi-core architectures have been shown to be an additional aid to this crusade of increased power-efficiency. Accelerators are growing in popularity as the next means of achieving power-efficient performance. Accelerators such as Intel SSE are ideal, but prove difficult to program. FPGAs, on the other hand, are less efficient due to their fine-grained reconfigurability. A middle ground is found in CGRAs, which are highly power-efficient, but largely programmable accelerators. Power-efficiencies of 100s of GOPs/W have been estimated, more than 2 orders of magnitude greater than current processors. Currently, CGRAs are limited in their applicability due to their ability to only accelerate a single thread at a time. This limitation becomes especially apparent as multi-core/multi-threaded processors have moved into the mainstream. This limitation is removed by enabling multi-threading on CGRAs through a software-oriented approach. The key capability in this solution is enabling quick run-time transformation of schedules to execute on targeted portions of the CGRA. This allows the CGRA to be shared among multiple threads simultaneously. Analysis shows that enabling multi-threading has very small costs but provides very large benefits (less than 1% single-threaded performance loss but nearly 300% CGRA throughput increase). By increasing dynamism of CGRA scheduling, system performance is shown to increase overall system performance of an optimized system by almost 350% over that of a single-threaded CGRA and nearly 20x faster than the same system with no CGRA in a highly threaded environment. Computer Science Computer Engineering Algorithms CGRA compilers power-efficiency Computer architecture Adaptive computing systems Embedded computer systems Improving CGRA utilization by enabling multi-threading for power-efficient embedded systems