Description
As machine learning (ML) continues to grow in popularity, the need for efficient hardware accelerators increases. Field Programmable Gate Arrays (FPGAs) have become a popular solution due to their reconfigurability. Network on Chips (NoCs) are a communication architecture gaining traction on FPGAs because they can quickly and efficiently connect different components. In this Thesis, we attempted to show that NoCs can be applied to machine learning on FPGAs. We connected matrix-vector multipliers to the NoC and implemented a simple multi-layer perceptron (MLP) across the different components. In this thesis, we were able to prove that using NoCs is a viable solution for accelerating machine learning and that there is opportunity to apply NoCs to larger machine learning designs.
Details
Contributors
- Lusenhop, Jacob (Author)
- Arora, Aman (Thesis director)
- Shrivastava, Aviral (Committee member)
- Barrett, The Honors College (Contributor)
- Computer Science and Engineering Program (Contributor)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2024-12
Topical Subject
Resource Type