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  4. Pre-Silicon Analysis of a Single Event Transient Pulse Measurement Test Structure in a FinFET Process
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Pre-Silicon Analysis of a Single Event Transient Pulse Measurement Test Structure in a FinFET Process

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Description

A Single Event Transient (SET) is a transient voltage pulse induced by an ionizing radiation particle striking a combinational logic node in a circuit. The probability of a storage element capturing the transient pulse depends on the width of the pulse. Measuring the rate of occurrence and the distribution of SET pulse widths is essential to understand the likelihood of soft errors and to develop cost-effective mitigation schemes. Existing research measures the pulse width of SETs in bulk Complementary Metal-Oxide-Semiconductor (CMOS) and Silicon On Insulator (SOI) technologies, but not on Fin Field-Effect Transistors (FinFETs). This thesis focuses on developing a test structure on the FinFET process to generate, propagate, and separate SETs and build a time-to-digital converter to measure the pulse width of SET.

The proposed SET test structure statistically separates SETs generated at NMOS and PMOS based on the difference in restoring current. It consists of N-collection devices to collect events at NMOS and P-collection devices to collect events at PMOS. The events that occur in PMOS of the N-collection device and NMOS of the P-collection device are false events. The logic gates of the collection devices are skewed to perform pulse expansion so that a minimally sustained SET propagates without getting suppressed by the contamination delay. A symmetric tree structure with an S-R latch event detector localizes the location of the SET. The Cartesian coordinates-based pulse injection structure injects external pulses at specific nodes to perform instrumentation and calibrate the measurement. A thermometer-encoded chain (vernier chain) with mismatched delay paths measures the width of the SET.

For low Linear Energy Transfer (LET) tests, the false events are entirely masked and do not propagate since the amount of charge that has to be deposited for successful event propagation is significantly high. In the case of high LET tests, the actual events and false events propagate, but they can be separated based on the SET location and the width of the output event. The vernier chain has a high measurement resolution of ~3.5ps, which aids in separating the events.

Date Created
2020
Contributors
  • Shreedharan, Sanjay (Author)
  • Brunhaver, John (Thesis advisor)
  • Clark, Lawrence (Committee member)
  • Sanchez Esqueda, Ivan (Committee member)
  • Arizona State University (Publisher)
Topical Subject
  • Computer Engineering
  • Electrical Engineering
  • SET Pulse Width Measurement
  • SET Test Structure
  • Vernier Chain
Resource Type
Text
Genre
Masters Thesis
Academic theses
Extent
75 pages
Language
eng
Copyright Statement
In Copyright
Primary Member of
ASU Electronic Theses and Dissertations
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.62784
Embargo Release Date
Mon, 08/01/2022 - 07:43
Level of coding
minimal
Note
Masters Thesis Electrical Engineering 2020
System Created
  • 2020-12-08 12:01:23
System Modified
  • 2021-08-26 09:47:01
  •     
  • 1 year 6 months ago
Additional Formats
  • OAI Dublin Core
  • MODS XML

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