Description
Caches have long been used to reduce memory access latency. However, the increased complexity of cache coherence brings significant challenges in processor design as the number of cores increases. While making caches scalable is still an important research problem, some researchers are exploring the possibility of a more power-efficient SRAM called scratchpad memories or SPMs.
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Contributors
- Cai, Jian (Author)
- Shrivastava, Aviral (Thesis advisor)
- Wu, Carole (Committee member)
- Ren, Fengbo (Committee member)
- Dasgupta, Partha (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2017
Resource Type
Collections this item is in
Note
- Doctoral Dissertation Computer Science 2017