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  4. A fast settling oversampled digital sliding-mode controller for DC-DC buck converters
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A fast settling oversampled digital sliding-mode controller for DC-DC buck converters

Full metadata

Description

Sliding-Mode Control (SMC) has several benefits over traditional Proportional-Integral-Differential (PID) control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. An All-Digital Sliding-Mode (ADSM) controlled DC-DC converter, utilizing single-bit oversampled frequency domain digitizers is proposed. In the proposed approach, feedback and reference digitizing Analog-to-Digital Converters (ADC) are based on a single-bit, first order Sigma-Delta frequency to digital converter, running at 32MHz over-sampling rate. The ADSM regulator achieves 1% settling time in less than 5uSec for a load variation of 600mA. The sliding-mode controller utilizes a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady state error (or DC offset), and limits the switching frequency range, which are the two common problems associated with sliding-mode controllers. The IC is designed and fabricated on a 0.35um CMOS process occupying an active area of 2.72mm-squared. Measured peak efficiency is 83%.

Date Created
2013
Contributors
  • Dashtestani, Ahmad (Author)
  • Bakkaloglu, Bertan (Thesis advisor)
  • Thornton, Trevor (Committee member)
  • Song, Hongjiang (Committee member)
  • Kiaei, Sayfe (Committee member)
  • Arizona State University (Publisher)
Topical Subject
  • Electrical Engineering
  • Buck Converter
  • DC-DC
  • Non-linear . .
  • PID
  • Sliding Mode
  • Electronic controllers
  • Sliding mode control
  • DC-to-DC converters
Resource Type
Text
Genre
Doctoral Dissertation
Academic theses
Extent
x, 63 p. : ill. (some col.)
Language
eng
Copyright Statement
In Copyright
Reuse Permissions
All Rights Reserved
Primary Member of
ASU Electronic Theses and Dissertations
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.20800
Embargo Release Date
Mon, 11/30/2015 - 19:39
Statement of Responsibility
by Ahmad Dashtestani
Description Source
Viewed on Mar. 4, 2014
Level of coding
full
Note
Partial requirement for: Ph.D., Arizona State University, 2013
Note type
thesis
Includes bibliographical references (p. 61-63)
Note type
bibliography
Field of study: Electrical engineering
System Created
  • 2014-01-31 11:30:05
System Modified
  • 2021-08-30 01:37:52
  •     
  • 1 year 5 months ago
Additional Formats
  • OAI Dublin Core
  • MODS XML

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