With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to aggressive architectural changes for on-chip power management and rapid development to energy efficient hardware accelerators.
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- Partial requirement for: M.S., Arizona State University, 2013Note typethesis
- Includes bibliographical references (p. 59-62)Note typebibliography
- Field of study: Electrical engineering