Description
With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to aggressive architectural changes for on-chip power management and rapid development to energy efficient hardware accelerators.
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Contributors
- Desai, Digant Pareshkumar (Author)
- Vrudhula, Sarma (Thesis advisor)
- Chakrabarti, Chaitali (Committee member)
- Wu, Carole-Jean (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2013
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Note
- Partial requirement for: M.S., Arizona State University, 2013Note typethesis
- Includes bibliographical references (p. 59-62)Note typebibliography
- Field of study: Electrical engineering
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Statement of Responsibility
by Digant Pareshkumar Desai