Full metadata
Title
SystemC TLM2.0 modeling of network-on-chip architecture
Description
Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction. SystemC TLM2.0 provides the capability to model hardware design at higher levels of abstraction with trade-off of simulation speed and accuracy. In this thesis, SystemC TLM2.0 models of NoC routers are developed at three levels of abstraction namely loosely-timed, approximately-timed, and cycle accurate. Simulation speed and accuracy of these three models are evaluated by a case study of a 4x4 mesh NoC.
Date Created
2012
Contributors
- Arlagadda Narasimharaju, Jyothi Swaroop (Author)
- Chatha, Karamvir S (Thesis advisor)
- Sen, Arunabha (Committee member)
- Shrivastava, Aviral (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
viii, 58 p. : ill. (some col.)
Language
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.14547
Statement of Responsibility
by Jyothi Swaroop Arlagadda Narasimharaju
Description Source
Viewed on Feb. 6, 2013
Level of coding
full
System Created
- 2012-08-24 06:16:01
System Modified
- 2021-08-30 01:48:43
- 2 years 3 months ago
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