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  2. Theses and Dissertations
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  4. UnSync: a soft error resilient redundant CMP architecture
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UnSync: a soft error resilient redundant CMP architecture

Full metadata

Description

Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are inevitable in the advancement of processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. This work proposes a novel customizable and redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. The inherent nature of UnSync architecture framework supports customization of the redundancy, and thereby provides means to achieve possible performance-reliability trade-offs in many-core systems. This work designs a detailed RTL model of UnSync architecture and performs hardware synthesis to compare the hardware (power/area) overheads incurred. It then compares the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. This work also performs cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, UnSync architecture reduces power consumption by 34.5% and improves performance by up to 20% with 13.3% less area overhead, when compared to Reunion architecture for the same level of reliability achieved.

Date Created
2011
Contributors
  • Hong, Fei (Author)
  • Shrivastava, Aviral (Thesis advisor)
  • Bazzi, Rida (Committee member)
  • Fainekos, Georgios (Committee member)
  • Arizona State University (Publisher)
Topical Subject
  • Computer Science
  • Chip Multiprocessors
  • Customizable
  • Redundant Execution
  • Reliable
  • Soft Error
  • UnSync
  • Redundancy (Engineering)
  • Microprocessors--Design and construction.
  • Microprocessors--Reliability.
  • Microprocessors
Resource Type
Text
Genre
Masters Thesis
Academic theses
Extent
iv, 32 p. : ill. (some col.)
Language
eng
Copyright Statement
In Copyright
Reuse Permissions
All Rights Reserved
Primary Member of
ASU Electronic Theses and Dissertations
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.8856
Statement of Responsibility
by Fei Hong
Description Source
Viewed on March 8, 2012
Level of coding
full
Note
Partial requirement for: M.S., Arizona State University, 2011
Note type
thesis
Includes bibliographical references (p. 31-32)
Note type
bibliography
Field of study: Computer science
System Created
  • 2011-08-12 03:28:47
System Modified
  • 2021-08-30 01:55:30
  •     
  • 1 year 6 months ago
Additional Formats
  • OAI Dublin Core
  • MODS XML

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