Threshold logic has long been studied as a means of achieving higher performance and lower power dissipation, providing improvements by condensing simple logic gates into more complex primitives, effectively reducing gate count, pipeline depth, and number of interconnects. This work proposes a new physical implementation of threshold logic, the threshold logic latch (TLL), which overcomes the difficulties observed in previous work, particularly with respect to gate reliability in the presence of noise and process variations.
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- Partial requirement for: Ph.D., Arizona State University, 2010Note typethesis
- Includes biblioghraphical references (p. 174-181)Note typebibliography
- Field of study: Computer science